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INTEGRATED CIRCUITS
I*CODE SL RC400
I*CODE Reader IC
Product Specification Revision 2.0 Preliminary
November 2001
Philips Semiconductors
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
CONTENTS 1 1.1 1.2 1.3 1.4 2 3 3.1 3.2 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 5 5.1 5.1.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.3 5.4 5.4.1 5.4.2 5.4.3 6 6.1 6.2 6.3 GENERAL INFORMATION..........................................................................................................6 Scope .........................................................................................................................................6 General Description.....................................................................................................................6 Features .....................................................................................................................................7 Ordering Information ....................................................................................................................7 BLOCK DIAGRAM ......................................................................................................................8 PINNING INFORMATION ............................................................................................................9 Pin Configuration .........................................................................................................................9 Pin Description.......................................................................................................................... 10 PARALLEL INTERFACE........................................................................................................... 12 Overview of Supported -Processor Interfaces ............................................................................ 12 Automatic -Processor Interface Type Detection.......................................................................... 12 Connection to Different -Processor Types ................................................................................. 13 Separated Read/Write Strobe: Intel Type Compatible................................................................... 13 Common Read/Write Strobe: Motorola Type Compatible.............................................................. 14 Common Read/Write Strobe and Hand-Shake Mechanism: EPP.................................................. 15 SL RC400 REGISTER SET........................................................................................................ 16 SL RC400 Registers Overview ................................................................................................... 16 Register Bit Behaviour ............................................................................................................... 18 Register Description................................................................................................................... 19 Page 0: Command and Status .................................................................................................... 19 Page 1: Control and Status ........................................................................................................ 27 Page 2: Transmitter and Control ................................................................................................. 33 Page 3: Receiver and Decoder Control ....................................................................................... 37 Page 4: RF-Timing and Channel Redundancy............................................................................. 43 Page 5: FIFO, Timer and IRQ- Pin Configuration ......................................................................... 48 Page 7: Test Control .................................................................................................................. 54 SL RC400 Register Flags Overview............................................................................................ 58 Modes of Register Addressing.................................................................................................... 61 Paging Mechanism .................................................................................................................... 61 Dedicated Address Bus.............................................................................................................. 61 Multiplexed Address Bus............................................................................................................ 61 MEMORY ORGANISATION OF THE EPROM ........................................................................... 62 Diagram of the EPROM Memory Organisation............................................................................ 62 Product Information Field (Read Only) ........................................................................................ 62 Register Initialisation Files (Read/Write) ...................................................................................... 63 2 Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
6.3.1 6.3.2 6.3.3 7 7.1 7.2 7.2.1 7.3 7.4 7.5 8 8.1 8.1.1 8.2 8.2.1 8.2.2 8.3 8.4 9 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.4 10 10.1 10.2 10.3 10.4 11
Start Up Register Initialisation File (Read/Write)........................................................................... 63 Shipment Content of Start Up Register initialisation File ............................................................... 64 Register Initialisation File (Read/Write)........................................................................................ 65 FIFO BUFFER........................................................................................................................... 66 Overview................................................................................................................................... 66 Accessing the FIFO Buffer.......................................................................................................... 66 Access Rules ............................................................................................................................ 66 Controlling the FIFO-Buffer......................................................................................................... 66 Status Information about the FIFO-Buffer.................................................................................... 67 Register overview FIFO Buffer.................................................................................................... 68 INTERRUPT REQUEST SYSTEM .............................................................................................. 69 Overview................................................................................................................................... 69 Interrupt Sources Overview........................................................................................................ 69 Implementation of Interrupt Request Handling ............................................................................. 70 Controlling Interrupts and their Status ......................................................................................... 70 Accessing the Interrupt Registers ............................................................................................... 70 Configuration of Pin IRQ ............................................................................................................ 70 Register Overview Interrupt Request System .............................................................................. 71 TIMER UNIT.............................................................................................................................. 72 Overview................................................................................................................................... 72 Implementation of the Timer Unit ................................................................................................ 73 Block Diagram........................................................................................................................... 73 Controlling the Timer Unit........................................................................................................... 74 Timer Unit Clock and Period....................................................................................................... 74 Status of the Timer Unit.............................................................................................................. 75 TimeSlotPeriod.......................................................................................................................... 75 Usage of the Timer Unit ............................................................................................................. 77 Time-Out- and Watch-Dog-Counter............................................................................................. 77 Stop Watch............................................................................................................................... 77 Programmable One-Shot Timer .................................................................................................. 77 Periodical Trigger ...................................................................................................................... 77 Register Overview Timer Unit..................................................................................................... 78 POWER REDUCTION MODES .................................................................................................. 79 Hard Power Down...................................................................................................................... 79 Soft Power Down....................................................................................................................... 79 Stand By Mode.......................................................................................................................... 80 Receiver Power Down................................................................................................................ 80 START UP PHASE.................................................................................................................... 81 3 Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
11.1 11.2 11.3 11.4 12 13 13.1
Hard Power Down Phase........................................................................................................... 81 Reset Phase.............................................................................................................................. 81 Initialising Phase........................................................................................................................ 81 Initialising the Parallel Interface-Type.......................................................................................... 82 OSCILLATOR CIRCUITRY........................................................................................................ 83 TRANSMITTER PINS TX1 AND TX2.......................................................................................... 84 Configuration of TX1 and TX2..................................................................................................... 84
13.2 Operating Distance versus Power Consumption .......................................................................... 84 13.2.1 Antenna Driver Output Source Resistance................................................................................... 85 13.3 13.4 14 14.1 14.2 Changing the Modulation Index .................................................................................................. 87 Pulse Width............................................................................................................................... 88 RECEIVER CIRCUITRY ............................................................................................................ 89 General..................................................................................................................................... 89 Block Diagram........................................................................................................................... 89
14.3 Putting the Receiver into Operation............................................................................................. 90 14.3.1 Automatic Clock-Q Calibration.................................................................................................... 90 14.3.2 Amplifier.................................................................................................................................... 91 14.3.3 Correlation Circuitry ................................................................................................................... 92 14.3.4 Evaluation and Digitizer Circuitry ................................................................................................ 92 15 15.1 15.2 15.3 16 16.1 16.2 SERIAL SIGNAL SWITCH......................................................................................................... 93 General..................................................................................................................................... 93 Block Diagram........................................................................................................................... 93 Registers Relevant for the Serial Signal Switch............................................................................ 94 SL RC400 COMMAND SET ....................................................................................................... 95 General Description................................................................................................................... 95 General Behaviour..................................................................................................................... 95
16.3 SL RC400 Commands Overview ................................................................................................ 96 16.3.1 Basic States.............................................................................................................................. 97 16.3.2 StartUp Command 3Fhex ............................................................................................................ 97 16.3.3 Idle Command 00hex ................................................................................................................... 97 16.4 Commands for Label Communication.......................................................................................... 98 16.4.1 Transmit Command 1A hex ........................................................................................................... 98 16.4.2 Receive Command 16hex .......................................................................................................... 100 16.4.3 Transceive Command 1E hex ..................................................................................................... 102 16.4.4 States of the Label Communication........................................................................................... 102 16.4.5 State Diagram for the Label Communication.............................................................................. 103 16.5 Commands to Access the EPROM .......................................................................................... 104 16.5.1 WriteE2 Command 01hex .......................................................................................................... 104 4 Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
16.5.2 ReadE2 Command 03hex .......................................................................................................... 106 16.6 Diverse Commands ................................................................................................................. 107 16.6.1 LoadConfig Command 07hex ..................................................................................................... 107 16.6.2 CalcCRC Command 12hex ........................................................................................................ 107 16.7 17 17.1 Error Handling during Command Execution ............................................................................... 108 TYPICAL APPLICATION......................................................................................................... 109 Circuit Diagram........................................................................................................................ 109
17.2 Circuit Description.................................................................................................................... 110 17.2.1 EMC Low Pass Filter ............................................................................................................... 110 17.2.2 Receiving Circuit...................................................................................................................... 110 17.3 Calculation of the Antenna Coil Inductance................................................................................ 110 17.3.1 Impedance Matching for Directly Matched Antennas .................................................................. 111 18 18.1 18.2 18.3 18.4 18.5 19 19.1 19.2 19.3 TEST SIGNALS ...................................................................................................................... 112 General................................................................................................................................... 112 Measurements Using the Serial Signal Switch........................................................................... 112 Analog Test-Signals................................................................................................................. 113 Digital Test-Signals.................................................................................................................. 114 Examples of Analog- and Digital Test Signals............................................................................ 115 ELECTRICAL CHARACTERISTICS......................................................................................... 117 Absolute Maximum Ratings ...................................................................................................... 117 Operating Condition Range...................................................................................................... 117 Current Consumption............................................................................................................... 117
19.4 Pin Characteristics .................................................................................................................. 118 19.4.1 Input Pin Characteristics .......................................................................................................... 118 19.4.2 Digital Output Pin Characteristics ............................................................................................. 119 19.4.3 Antenna Driver Output Pin Characteristics ................................................................................ 119 19.5 AC Electrical Characteristics .................................................................................................... 120 19.5.1 AC Symbols ............................................................................................................................ 120 19.5.2 AC Operating Specification....................................................................................................... 121 19.5.3 Clock Frequency ..................................................................................................................... 124 20 21 21.1 22 23 24 25 E PROM CHARACTERISTICS ................................................................................................ 125 PACKAGE OUTLINES ............................................................................................................ 126 SO32 ...................................................................................................................................... 126 TERMS AND ABBREVIATIONS .............................................................................................. 127 DEFINITIONS ......................................................................................................................... 128 LIFE SUPPORT APPLICATIONS............................................................................................. 128 REVISION HISTORY............................................................................................................... 129 5 Preliminary
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Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
1 1.1
GENERAL INFORMATION Scope
This document describes the functionality of the SL RC400. It includes the functional and electrical specifications and gives details on how to design-in this device from system and hardware viewpoint.
1.2
General Description
The SL RC400 is member of a new family of highly integrated reader ICs for contactless communication at 13.56 MHz. This new reader IC family utilises an outstanding modulation and demodulation concept completely integrated for all kinds of passive contactless communication methods and protocols at 13.56 MHz. The SL RC400 supports all layers of I*CODE1 and ISO 15693. The internal transmitter part is able to drive an antenna designed for proximity operating distance (up to 100 mm) directly without additional active circuitry. The receiver part provides a robust and efficient implementation of a demodulation and decoding circuitry for signals from I*CODE1 and ISO 15693 compatible transponders. The digital part handles I*CODE1 and ISO 15693 framing and error detection (CRC). A comfortable parallel interface which can be directly connected to any 8-bit -Processor gives high flexibility for the reader/terminal design.
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Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
1.3 * * * * * * * * * * * * * * * * * *
Features Highly integrated analog circuitry to demodulate and decode label response Buffered output drivers to connect an antenna with minimum number of external components Proximity operating distance (up to 100 mm) Supports I*CODE1 and ISO 15693 Parallel -Processor interface with internal address latch and IRQ line Flexible interrupt handling Automatic detection of parallel C interface type Comfortable 64 byte send and receive FIFO-buffer Hard reset with low power function Power down mode per software Programmable timer Unique serial number User programmable start-up configuration Bit- and byte-oriented framing Independent power supply pins for digital, analog and transmitter part Internal oscillator buffer to connect 13.56 MHz quartz, optimised for low phase jitter Clock frequency filtering 3.3 V operation for transmitter (antenna driver) in short range applications
1.4
Ordering Information Package Name SO32 Description Small Outline Package; 32 leads Table 1-1: SL RC400 Ordering Information
Type Number SL RC400 01T
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Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
2
BLOCK DIAGRAM
N_WR, N_RD, N_CS
ALE
A0, A1, A2
D0 to D7
Parallel Interface Control
(incl. Automatic Interface Detection & Synchronisation)
Voltage Monitor & Power On Detect State Machine Reset Control
DVDD
DVSS
FIFO Control
64 Byte FIFO
Command Register
Programable Timer
Power Down Control
RSTPD
Control Register Bank Interrupt Control
IRQ
EEPROM 8 x 16 Byte EEPROM Access Control
CRC16/CRC8 Generation & Check
Parallel/Seriell Converter
Bit Counter
Parity Generation & Check
Frame Generation & Check
Bit Decoding
Bit Coding
Serial Data Switch
SIGOUT
Level Shifters
Amplitude Rating Correlation and Bit Decoding Reference Voltage
Clock Generation, Filtering and Distribution
OSCIN
Oscillator
OSCOUT
Q-Clock Generation
Power On Detect
AVDD AVSS
Analog Test MUX
I-Channel Amplifier I-Channel Demodulator
Q-Channel Amplifier Q-Channel Demodulator
Transmitter Control
GND
V+
GND
V+
VMID
AUX
RX TVSS TX1 TX2 TVDD
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Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
3 3.1
PINNING INFORMATION Pin Configuration
Pins denoted by bold letters are supplied by AVDD and AVSS. Pins drawn with bold lines are supplied by TVSS and TVDD. All other pins are supplied by DVDD and DVSS.
OSCIN
1
32
OSCOUT
IRQ
2
31
RSTPD
RFU
3
30
VMID RX
SIGOUT
4
29
TX1
5
28
AVSS
TVDD
6
27
AUX
TX2
7
26
AVDD
TVSS
8
NCS
9
SL RC400 SO32
25
DVDD
24
A2
NWR
10
23
A1
NRD
11
22
A0
DVSS
12
21
ALE
D0
13
20
D7
D1
14
19
D6
D2
15
18
D5
D3
16
17
D4
Figure 3-1: SL RC400 Pin Configuration for SO32 package
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Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
3.2
Pin Description O...Output; PWR...Power
Pin Types: I...Input;
PIN 1 2 3 4 5 6 7 8 9 10
1
SYMBOL OSCIN IRQ RFU SIGOUT TX1 TVDD TX2 TVSS NCS NWR R/NW nWrite NRD
TYPE I O I O O PWR O PWR I I I I I I I PWR I/O I/O I I I I O I I PWR PWR
DESCRIPTION Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is also the input for an externally generated clock (fosc = 13.56 MHz). Interrupt Request: output to signal an interrupt event This Pin should be connected to Ground
I*CODE Interface Output: delivers a serial data stream according to I*CODE1 and
ISO 15693 Transmitter 1: delivers the modulated 13.56 MHz carrier frequenzy Transmitter Power Supply: supplies the output stage of TX1 and TX2 Transmitter 2: delivers the modulated 13.56 MHz carrier frequenzy Transmitter Ground: supplies the output stage of TX1 and TX2 Not Chip Select: selects and activates the -Processor interface of the SL RC400 Not Write: strobe to write data (applied on D0 to D7) into the SL RC400 register Read Not Write: selects if a read or write cycle shall be performed. Not Write: selects if a read or write cycle shall be performed Not Read: strobe to read data from the SL RC400 register (applied on D0 to D7) Not Data Strobe: strobe for the read and the write cycle Not Data Strobe: strobe for the read and the write cycle Digital Ground 8 Bit Bi-directional Data Bus 8 Bit Bi-directional Address and Data Bus Address Latch Enable: strobe signal to latch AD0 to AD5 into the internal address latch when HIGH. Address Strobe: strobe signal to latch AD0 to AD5 into the internal address latch when HIGH. Not Address Strobe: strobe signal to latch AD0 to AD5 into the internal address latch when LOW. Address Line 1: Bit 0 of register address Not Wait: signals with LOW that an access-cycle may started and with HIGH that it may be finished. Address Line 1: Bit 1 of register address Address Line 2: Bit 2 of register address Digital Power Supply Analog Power Supply
11
1
NDS nDStrb DVSS D0 to D7 AD0 to AD7 ALE
12 13 ... 201
211
AS nAStrb A0
221 23 24 25 26
nWait A1 A2 DVDD AVDD
1
These pins offer different functionality according to the selected -Processor interface type. For detailed information refer to chapter 4.
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Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
PIN Description (continued)
PIN 27 28 29 30
SYMBOL AUX AVSS RX VMID
TYPE O PWR I PWR
DESCRIPTION Auxiliary Output: This pin delivers analog test signals. The signal delivered on this output may be selected by means of the TestAnaOutSel Register. Analog Ground Receiver Input: Input pin for the labels response, which is the load modulated 13.56 MHz carrier frequenzy, that is coupled out from the antenna circuit. Internal Reference Voltage: This pin delivers the internal reference voltage. Note: It has to be supported by means of a 100 nF block capacitor. Reset and Power Down: When HIGH, internal current sinks are switched off, the oscillator is inhibited, and the input pads are disconnected from the outside world. With a negative edge on this pin the internal reset phase starts. Crystal Oscillator Output: Output of the inverting amplifier of the oscillator.
31 32
RSTPD OSCOUT
I O
Table 3-1: SL RC400 Pin Description
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Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
4 4.1
PARALLEL INTERFACE Overview of Supported -Processor Interfaces
The SL RC400 supports direct interfacing of various -Processor. Alternatively the Enhanced Parallel Port (EPP) of personal computers can be connected directly. The following table shows the parallel interface signals supported by the SL RC400:
Bus Control Signals Bus control Separated Read and Write Strobes address data control Common Read and Write Strobe address data control Common Read and Write Strobe with Handshake (EPP) data AD0 ... AD7 address Separated Address and Data Bus NRD, NWR, NCS A0, A1, A2 D0 ... D7 R/NW, NDS, NCS A0, A1, A2 D0 ... D7 Multiplexed Address and Data Bus NRD, NWR, NCS, ALE AD0, AD1, AD2, (AD3, AD4, AD5) AD0 ... AD7 R/NW, NDS, NCS, AS AD0, AD1, AD2, (AD3, AD4, AD5) AD0 ... AD7 nWrite, nDStrb, NCS, nAStrb, nWait AD0, AD1, AD2, (AD3, AD4, AD5)
Table 4-1: Supported -Processor Interface Signals
4.2
Automatic -Processor Interface Type Detection
After each Power-On or Hard Reset, the SL RC400 also resets its parallel -Processor interface mode and checks the current -Processor interface type. The SL RC400 identifies the -Processor interface by means of the logic levels on the control pins after the Reset Phase. This is done by a combination of fixed pin connections (see below) and a dedicated initialisation routine (see 11.4).
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Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
4.3
Connection to Different -Processor Types
The connection to different -Processor types is shown in the following table:
Parallel Interface Type Separated Read/Write Strobe SL RC400 Dedicated Address Bus ALE A2 A1 A0 NRD NWR NCS D7 ... D0 HIGH A2 A1 A0 NRD NWR NCS D7 ... D0 Multiplexed Address Bus ALE LOW HIGH HIGH NRD NWR NCS AD7 ... AD0 Dedicated Address Bus HIGH A2 A1 A0 NDS R/NW NCS D7 ... D0 Multiplexed Address Bus AS LOW HIGH LOW NDS R/NW NCS AD7 ... AD0 Common Read/Write Strobe Multiplexed Address Bus with Handshake nAStrb HIGH HIGH nWait nDStrb nWrite LOW AD7 ... AD0
Table 4-2: Connection Scheme for Detecting the Parallel Interface Type
4.3.1
SEPARATED READ/WRITE STROBE: INTEL TYPE COMPATIBLE
SL RC400
Address Bus (A3...An) Address Decoder
SL RC400
Non Multiplexed Address Address Decoder
NCS
NCS
LOW Address Bus (A0...A2)
A0...A2
HIGH HIGH
A2 A1 A0
Data Bus (D0...D7)
D0...D7
Multiplexed Address/Data (AD0...AD7)
D0...D7
HIGH
ALE
Read Strobe (NRD)
Address Latch Enable (ALE)
ALE NRD NWR
NRD NWR
Read Strobe (NRD)
Write Strobe (NWR)
Write Strobe (NWR)
Figure 4-1: Connection to -Processors with Separated Read/Write Strobes
For timing specification refer to chapter 19.5.2.1. 13 Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
4.3.2
COMMON READ/WRITE STROBE: MOTOROLA TYPE COMPATIBLE
SL RC400
Address Bus (A3...An) Address Decoder
SL RC400
Non Multiplexed Address Address Decoder
NCS
NCS
LOW Address Bus (A0...A2)
A0...A2
HIGH LOW
A2 A1 A0 D0...D7
Data Bus (D0...D7)
D0...D7
Multiplexed Address/Data (AD0...AD7)
HIGH
ALE NRD NWR
Address Strobe (AS)
ALE NRD NWR
Data Strobe (NDS)
Data Strobe (NDS)
Read/Write (R/NW)
Read/Write (R/NW)
Figure 4-2: Connection to -Processors with Common Read/Write Strobes For timing specification refer to chapter 19.5.2.2.
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Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
4.3.3
COMMON READ/WRITE STROBE AND HAND-SHAKE MECHANISM: EPP
SL RC400
LOW
NCS
HIGH HIGH nWait
A2 A1 A0
Multiplexed Address/Data (AD1...AD8)
D0...D7
Address Strobe (nAStrb)
ALE NRD NWR
Data Strobe (nDStrb)
Read/Write (nWrite)
Figure 4-3: Connection to -Processors with Common Read/Write Strobes and Hand-Shake
For timing specification refer to chapter 19.5.2.3. Remarks for EPP: Although in the standard for the EPP no chip select signal is defined, the N_CS of the SL RC400 allows inhibiting the nDStrb signal. If not used, it shall be connected to DVSS. After each Power-On or Hard Reset the nWait signal (delivered at pin A0) is high impedance. nWait will be defined at the first negative edge applied to nAStrb after the Reset Phase. The SL RC400 does not support Read Address Cycle.
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Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5 5.1
SL RC400 REGISTER SET SL RC400 Registers Overview
Addresshex 0 1 2 3 4 5 6 7 8 9 A B C D E F Page 2: Transmitter and Coder Control 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Register Name Page Command FIFOData PrimaryStatus FIFOLength SecondaryStatus InterruptEn InterruptRq Page Control ErrorFlag Collpos TimerValue CRCResultLSB CRCResultMSB PreSet0F Page TxControl CwConductance ModConductance CoderControl ModWidth ModWidthSOF PreSet17 Page RxControl1 DecoderControl BitPhase RxThreshold PreSet1D RxControl2 ClockQControl Function selects the register page starts (and stops) the command execution in- and output of 64 byte FIFO buffer status flags of the receiver and transmitter and of the FIFO buffer number of bytes buffered in the FIFO diverse status flags control bits to enable and disable passing of interrupt requests interrupt request flags selects the register page diverse control flags e.g.: timer, power saving error flags showing the error status of the last command executed bit position of the first bit collision detected on the RF-interface actual value of the timer LSB of the CRC-Coprocessor register MSB of the CRC-Coprocessor register these values shall not be changed selects the register page controls the logical behaviour of the antenna driver pins TX1 and TX2 selects the conductance of the antenna driver pins TX1 and TX2 selects the conductance of the antenna driver pins TX1 and TX2 during modulation Selects the bit coding mode and the framing during transmission selects the width of the modulation pulse selects the width of the modulation pulse for SOF (I*CODE Fast-Mode) these values shall not be changed selects the register page controls receiver behaviour controls decoder behaviour selects the bit-phase between transmitter and receiver clock selects thresholds for the bit decoder these values shall not be changed controls decoder behaviour and defines the input source for the receiver controls clock generation for the 90 phase shifted Q-channel clock
Page Page 0: Command and Status Page 3: Receiver and Decoder Control Page 1: Control and Status
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Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
SL RC400 Register Set (continued)
Page Page 4: RF-Timing and Channel Redundancy Addresshex 20 21 22 23 24 25 26 27 Page 5: FIFO, Timer and IRQPin Configuration 28 29 2A 2B 2C 2D 2E 2F 30 31 32 Page 6: RFU 33 34 35 36 37 38 39 Page 7: Test Control 3A 3B 3C 3D 3E 3F Register Name Page RxWait ChannelRedundancy CRCPresetLSB CRCPresetMSB TimeSlotPeriod SIGOUTSelect PreSet27 Page FIFOLevel TimerClock TimerControl TimerReload IrqPinConfig PreSet2E PreSet2F Page RFU RFU RFU RFU RFU RFU RFU Page RFU TestAnaSelect PreSet3B PreSet3C TestDigiSelect RFU RFU Function selects the register page selects the time interval after transmission, before receiver starts selects the kind and mode of checking the data integrity on the RFchannel LSB of the pre-set value for the CRC register MSB of the pre-set value for the CRC register selects the time between automatically mitted Frames see chapter 9.2.5 selects internal signal applied to pin SIGOUT includes the MSB of value TimeSlotPeriod see register 0x25 these values shall not be changed Selects the register page defines level for FIFO over- and underflow warning selects the divider for the timer clock selects start and stop conditions for the timer defines the pre-set value for the timer configures the output stage of pin IRq these values shall not be changed these values shall not be changed selects the register page reserved for future use reserved for future use reserved for future use reserved for future use reserved for future use reserved for future use reserved for future use selects the register page reserved for future use selects analog test mode these values shall not be changed these values shall not be changed selects digital test mode reserved for future use reserved for future use
Table 5-1: SL RC400 Register Overview
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Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.1.1
REGISTER BIT BEHAVIOUR
Bits and flags for different registers behave differently, depending on their functions. In principle bits with same behaviour are grouped in common registers.
Abbreviation
Behaviour read and write
Description These bits can be written and read by the -Processor. Since they are used only for control means, there content is not influenced by internal state machines, e.g. the TimerReload-Register may be written and read by the Processor. It will also be read by internal state machines, but never changed by them. These bits can be written and read by the -Processor. Nevertheless, they may also be written automatically by internal state machines, e.g. the CommandRegister changes its value automatically after the execution of the actual command. These registers hold flags, which value is determined by internal states only, e.g. the ErrorFlag-Register can not be written from external but shows internal states. These registers are used for control means only. They may be written by the Processor but can not be read. Reading these registers returns an undefined value, e.g. the TestAnaSelect-Register is used to determine the signal on pin AUX, but it is not possible to read its content.
r/w
dy
dynamic
r
read only
w
write only
Table 5-2: Behaviour of Register Bits and its Designation
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Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2 5.2.1
Register Description PAGE 0: COMMAND AND STATUS Page Register
5.2.1.1
Selects the register page. Name: Page Address: 0x00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30, 0x38 Reset value: 10000000, 0x80
7 UsePage Select Access Rights r/w
6 0 r/w
5 0 r/w
4 0 r/w
3 0 r/w
2
1 PageSelect
0
r/w
r/w
r/w
Description of the bits Bit 7 Symbol UsePageSelect Function If set to 1, the value of PageSelect is used as register address A5, A4, and A3. The LSBbits of the register address are defined by the address pins or the internal address latch, respectively. If set to 0, the whole content of the internal address latch defines the register address. The address pins are used as described in Table 4-2. Reserved for future use. The value of PageSelect is used only if UsePageSelect is set to 1. In this case, it specifies the register page (which is A5, A4, and A3 of the register address).
6-3 2-0
0000 PageSelect
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.1.2
Command Register
Starts and stops the command execution. Name: Command 7 IFDetect Busy Access Rights r 6 0 r dy dy 5 Address: 0x01 4 3 Command dy dy dy dy Reset value:X0000000, 0xX0 2 1 0
Description of the bits Bit 7 Symbol IFDetectBusy Function Shows the status of Interface Detection Logic: Set to 0 means `Interface Detection finished successfully', Set to 1 signs `Interface Detection Ongoing'. Reserved for future use. Activates a command according the Command Code. Reading this register shows, which command is actually executed. See chapter 16. SL RC400 Command Set.
6 5-0
0 Command
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.1.3
FIFOData Register
In- and output of the 64 byte FIFO buffer Name: FIFOData Address: 0x02 Reset value: XXXXXXXX, 0xXX
7
6
5
4 FIFOData
3
2
1
0
Access Rights
dy
dy
dy
dy
dy
dy
dy
dy
Description of the bits Bit 7-0 Symbol FIFOData Function Data Input and Output Port for the internal 64 byte FIFO buffer. The FIFO buffer acts as parallel in/parallel out converter for all data stream in- and outputs.
21
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.1.4
PrimaryStatus Register
Status flags of the receiver, transmitter and the FIFO buffer. Name: PrimaryStatus 7 0 Access Rights r r 6 Address: 0x03 5 ModemState r r 4 3 IRq r Reset value: 00000001, 0x01 2 Err r 1 HiAlert r 0 LoAlert r
Description of the bits Bit 7 6-4 Symbol 0 ModemState Reserved for future use. ModemState shows the state of the transmitter and receiver state machines. Function
State 000
Name of State Idle
Description Neither the transmitter nor the receiver is in operation, since none of them is started or since none of them has got input data. Transmitting the `Start Of Frame' Pattern. Transmitting data from the FIFO buffer (or redundancy check bits). Transmitting the `End Of Frame' Pattern. Mean-State passed, when receiver starts. Mean-State passed, when receiver finishes. Waiting until the time period selected in the RxWait Register has expired. Receiver activated; Awaiting an input signal at pin Rx. Receiving data.
001 010 011 100
TxSOF TxData TxEOF GoToRx1 GoToRx2
101 110 111
PrepareRx AwaitingRx Receiving
3 2 1
IRq Err HiAlert
This bit shows, if any interrupt source requests attention (with respect to the setting of the interrupt enable flags in the InterruptEn Register). This bit is set to 1, if any error flag in the ErrorFlag Register is set. Is set to 1, when the number of bytes stored in the FIFO buffer fulfil the following equation: HiAlert = (64 - FIFOLength) WaterLevel
Example: FIFOLength=60, WaterLevel=4 FIFOLength=59, WaterLevel=4 HiAlert =1 HiAlert =0
0
LoAlert
Is set to 1, when the number of bytes stored in the FIFO buffer fulfil the following equation: LoAlert = FIFOLength WaterLevel
Example: FIFOLength=4, WaterLevel=4 FIFOLength=5, WaterLevel=4 LoAlert =1 LoAlert =0
22
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.1.5
FIFOLength Register
Number of bytes buffered in the FIFO. Name: FIFOLength 7 0 Access Rights r r r r 6 Address: 0x04 5 4 3 FIFOLength r r r r Reset value: 00000000, 0x00 2 1 0
Description of the bits Bit 7 6-0 Symbol 0 FIFOLength Reserved for future use. Indicates the number of bytes stored in the FIFO buffer. Writing to the FIFOData Register increments, reading decrements FIFOLength. Function
23
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.1.6
SecondaryStatus Register
Diverse Status flags. Name: SecondaryStatus 7 TRunning Access Rights r 6 E2Ready r Address: 0x05 5 CRCReady r 4 0 r 3 0 r r Reset value: 01100000, 0x60 2 1 RxLastBits r r 0
Description of the bits Bit 7 6 5 4-3 2-0 Symbol TRunning E2Ready CRCReady 00 RxLastBits Function If set to 1, the SL RC400's timer unit is running, e.g. the counter will decrement the Timer Value Register with the next timer clock. If set to 1, the SL RC 400 has finished programming the E PROM. If set to 1, the SL RC400 has finished calculating the CRC. Reserved for future use. Show the number of valid bits in the last received byte. If zero, the whole byte is valid.
2
24
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.1.7
InterrupEn Register
Control bits to enable and disable passing of interrupt requests. Name: InterruptEn 7 SetIEn Access Rights w 6 0 r/w Address: 0x06 5 TimerIEn r/w 4 TxIEn r/w 3 RxIEn r/w Reset value: 00000000, 0x00 2 IdleIEn r/w 1 HiAlertIEn r/w 0 LoAlertIEn r/w
Description of the bits Bit 7 6 5 4 Symbol SetIEn 0 TimerIEn TxIEn Function Set to 1 SetIEn defines that the marked bits in the InterruptEn Register are set, Set to 0 clears the marked bits. Reserved for future use. Allows the timer interrupt request (indicated by bit TimerIRq) to be propagated to pin IRQ. This bit can not be set or cleared directly but only by means of bit SetIEn. Allows the transmitter interrupt request (indicated by bit TxIRq) to be propagated to pin IRQ. This bit can not be set or cleared directly but only by means of bit SetIEn. Allows the receiver interrupt request (indicated by bit RxIRq) to be propagated to pin IRQ. This bit can not be set or cleared directly but only by means of bit SetIEn. Allows the idle interrupt request (indicated by bit IdleIRq) to be propagated to pin IRQ. This bit can not be set or cleared directly but only by means of bit SetIEn. Allows the high alert interrupt request (indicated by bit HiAlertIRq) to be propagated to pin IRQ. This bit can not be set or cleared directly but only by means of bit SetIEn. Allows the low alert interrupt request (indicated by bit LoAlertIRq) to be propagated to pin IRQ. This bit can not be set or cleared directly but only by means of bit SetIEn.
3 2 1
RxIEn IdleIEn HiAlertIEn
0
LoAlertIEn
25
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.1.8
InterruptRq Register
Interrupt request flags. Name: InterruptRq 7 SetIRq Access Rights w 6 0 r/w Address: 0x07 5 TimerIRq dy 4 TxIRq dy 3 RxIRq dy Reset value: 00000000, 0x00 2 IdleIRq dy 1 HiAlertIRq dy 0 LoAlertIRq dy
Description of the bits Bit 7 6 5 4 Symbol SetIRq 0 TimerIRq TxIRq Function Set to 1 SetIRq defines that the marked bits in the InterruptRq Register are set. Set to 0 defines, that the marked bits in the InterruptRq Register are cleared. Reserved for future use. Set to 1, when the timer decrements the TimerValue Register to zero. Set to 1, when one of the following events occurs: Transceive Command: All data transmitted. CalcCRC Command: All data is processed. WriteE2 Command: All data is programmed. 3 2 RxIRq IdleIRq This bit is set to 1, when the receiver terminates. This bit is set to 1, when a command terminates by itself e.g. when the Command Register changes its value from any command to the Idle Command. If an unknown command is started bit IdleIRq is set. Starting the Idle Command by the -Processor does not set bit IdleIRq. This bit is set to 1, when bit HiAlert is set. In opposite to HiAlert, HiAlertIRq stores this event and can only be reset by means of bit SetIRq. This bit is set to 1, when bit LoAlert is set. In opposite to LoAlert, LoAlertIRq stores this event and can only be reset by means of bit SetIRq.
1 0
HiAlertIRq LoAlertIRq
26
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.2 5.2.2.1
PAGE 1: CONTROL AND STATUS Page Register
Selects the register page. See 5.2.1.1 Page register.
5.2.2.2
Control Register
Diverse control flags, e.g. : timer, power saving Name: Control Address: 0x09 Reset value: 00000000, 0x00
7 0 Access Rights r/w
6 0 r/w
5 StandBy dy
4 PowerDown dy
3 0 dy
2 TStopNow w
1 TStartNow w
0 FlushFIFO w
Description of the bits Bit 7-6 5 4 3 2 1 0 Symbol 00 StandBy PowerDown 0 TStopNow TStartNow FlushFIFO Reserved for future use Setting this bit to 1 enters the Soft PowerDown Mode. This means, internal current consuming blocks switch off, the oscillator keeps running. Setting this bit to 1 enters the Soft PowerDown Mode. This means, internal current consuming blocks switch off including the oscillator. Reserved for future use Setting this bit to 1 starts the timer immediately. Reading this bit will always return 0. Setting this bit to 1 stops the timer immediately. Reading this bit will always return 0. Setting this bit to 1clears the internal FIFO-buffer's read- and write-pointer (FIFOLength becomes 0) and the flag FIFOOvfl immediately. Reading this bit will always return 0. Function
27
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.2.3
ErrorFlag Register
Error flags showing the error status of the last executed command. Name: ErrorFlag Address: 0x0A Reset value: 00000000, 0x00
7 0 Access Rights r
6 0 r
5 AccessErr r
4 FIFOOvfl r
3 CRCErr r
2 FramingErr r
1 0 r
0 CollErr r
Description of the bits Bit 7-6 5 4 Symbol 0 AccessErr FIFOOvfl Reserved for future use. This bit is set to 1, if the access rights to the EPROM are violated. This bit is set to 0 starting an EPROM related command. This bit is set to 1, if the -Processor or a SL RC400's internal state machine (e.g. receiver) tries to write data into the FIFO buffer although the FIFO buffer is already full. This bit is set to 1, if RxCRCEn is set and the CRC fails. It is cleared to 0 automatically at receiver start phase during the state PrepareRx. This bit is set to 1, if the SOF is incorrect. It is cleared automatically at receiver start (that is during the state PrepareRx). RFU This bit is set to 1, if a bit-collision is detected. It is cleared automatically at receiver start (that is during the state PrepareRx). Function
3 2 1 0
CRCErr FramingErr 0 CollErr
28
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.2.4
CollPos Register
Bit position of the first bit collision detected on the RF- interface. Name: CollPos Address: 0x0B Reset value: 00000000, 0x00
7
6
5
4 CollPos
3
2
1
0
Access Rights
r
r
r
r
r
r
r
r
Description of the bits Bit 7-0 Symbol CollPos Function This register shows the bit position of the first detected collision in a received frame. Example: 0x00 indicates a bit collision in the start bit 0x01 indicates a bit collision in the 1 bit 0x08 indicates a bit collision in the 8 bit
th st
29
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.2.5
TimerValue Register
Actual value of the timer Name: TimerValue Address:0x0C Reset value: XXXXXXXX, 0xXX
7
6
5
4 TimerValue
3
2
1
0
Access Rights
r
r
r
r
r
r
r
r
Description of the bits
Bit 7-0 Symbol TimerValue Function
This register shows the actual value of the timer counter.
30
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.2.6
CRCResultLSB Register
LSB of the CRC-Coprocessor register.
Name: CRCResultLSB
Address: 0x0D
Reset value: XXXXXXXX, 0xXX
7
6
5
4
3
2
1
0
CRCResultLSB Access Rights r r r r r r r r
Description of the bits Bit 7-0 Symbol CRCResultLSB Function This register shows the actual value of the least significant byte of the CRC register. It is valid only if bit CRCReady is set to 1.
31
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.2.7
CRCResultMSB Register
MSB of the CRC-Coprocessor register.
Name: CRCResultMSB
Address: 0x0E
Reset value: XXXXXXXX, 0xXX
7
6
5
4
3
2
1
0
CRCResultMSB Access Rights r r r r r r r r
Description of the bits Bit 7-0 Symbol CRCResultMSB Function This register shows the actual value of the most significant byte of the CRC register. It is valid only if bit CRCReady is set to 1. For 8-bit CRC calculation the registers value is undefined.
5.2.2.8
PreSet0F Register Address: 0x0F Reset value: 00000000, 0x00
Name: PreSet0F
7 0 Access Rights r/w
6 0 r/w
5 0 r/w
4 0 r/w
3 0 r/w
2 0 r/w
1 0 r/w
0 0 r/w
Note: These values shall not be changed !
32
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.3 5.2.3.1
PAGE 2: TRANSMITTER AND CONTROL Page Register
Selects the register page. See 5.2.1.1 Page register.
5.2.3.2
TxControl Register
Controls the logical behaviour of the antenna pin TX1 and TX2 Name: TxControl Address: 0x11 Reset value: 01001000, 0x48
7 0 Access Rights r/w
6
5
4 Force100 ASK r/w
3 TX2Inv r/w
2 TX2Cw r/w
1 TX2RFEn r/w
0 TX1RFEn r/w
ModulatorSource r/w r/w
Description of the bits Bit 7 6-5 Symbol 0 Modulator Source This value shall not be changed Selects the source for the modulator input: 00: 01: 10: 11: 4 3 2 Force100ASK TX2Inv TX2Cw LOW HIGH Internal Coder RFU Function
Set to 1, forces a 100% ASK Modulation independent of the setting in the ModConductance Register. Set to 1, the output signal on pin TX2 will deliver an inverted 13.56 MHz carrier frequenzy. Set to 1, the output signal on pin TX2 will deliver continuously the un-modulated 13.56 MHz carrier frequenzy. Setting TX2Cw to 0 enables modulation of the 13.56 MHz carrier frequenzy.
1
TX2RFEn
Set to 1, the output signal on pin TX2 will deliver the 13.56 MHz carrier frequency modulated by the transmission data. If TX2RFEn is 0, TX2 drives a constant output level. See chapter 13.
0
TX1RFEn
Set to 1, the output signal on pin TX1 will deliver the 13.56 MHz carrier frequency modulated by the transmission data. If TX1RFEn is 0, TX1 drives a constant output level. See chapter 13.
33
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.3.3
CwConductance Register
Selects the conductance of the antenna driver pins TX1 and TX2. Name: CwConductance Address: 0x12 Reset value: 00111111, 0x3F
7 0 Access Rights r/w
6 0 r/w
5
4
3 GsCfgCW
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
Description of the bits Bit 7-6 5-0 Symbol 00 GsCfgCW These values shall not be changed The value of this register defines the conductance of the output driver. This may be used to regulate the output power and subsequently current consumption and operating distance. Function
For detailed information about GsCfgCW see 13.2.1
5.2.3.4
ModConductance Register Address: 0x13 Reset value: 00000101, 0x05
Name: ModConductance
7 0 Access Rights r/w
6 0 r/w
5
4
3 GsCfgMod
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
Description of the bits Bit 7-6 5-0 Symbol 00 GsCfgMod These values shall not be changed The value of this register defines the conductance of the output driver for the time of modulation. This may be used to regulate the modulation index. Function
For detailed information about GsCfgMod see 13.3
34
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.3.5
CoderControl Register Address:0x14 Reset value: 00101100, 0x2C
Name: CoderControl
7 SendOne Pulse Access Rights r/w
6 0 r/w
5
4 CoderRate
3
2
1 TxCoding
0
r/w
r/w
r/w
r/w
r/w
r/w
Description of the bits Bit 7 Symbol SendOnePulse Function Set to 1, forces to generate only one Mudulation (for ISO 15693 only). This is used to switch to the next TimeSlot if the Inventory command is used. This bit is not cleared automatically, it has to be re-set to 0 by the user. These values shall not be changed This register defines the clock rate for Coder Circuit 000: 001: 010: 011: 100: 101: 110: 111: 2-0 TxCoding RFU RFU RFU RFU RFU For I?CODE1 standard mode and ISO 15693 (~52.97kHz) For I?CODE1 fast mode (~26.48kHz) RFU
6 5-3
0 CoderRate
This register defines the bit coding Mode and Framing during Transmission 000: 001: 010: 011: 100: 101: 110: 111: RFU RFU RFU RFU For I?CODE1 standard mode (1 out of 256 coding) For I?CODE1 fast mode (RZ coding) For ISO 15693 standard mode (1 out of 256 coding) For ISO 15693 fast mode (1 out of 4 coding)
35
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.3.6
ModWidth Register
selects the width of the modulation pulse. Name: ModWidth Address: 0x15 Reset value: 00111111, 0x3F
7
6
5
4 ModWidth
3
2
1
0
Access Rights
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Description of the bits Bit 7-0 Symbol ModWidth Function This register defines the width of the modulation pulse according to Tmod = 2(ModWidth +1) / fc (fc = Oscillator clock 13.56 MHz). Preset for I*CODE1 (Fast and Standard Mode) and ISO 15693 is 0x3F (Modulation width: 9.44s).
5.2.3.7
ModWidthSOF Register Address: 0x16 Reset value: 00111111, 0x3F
Name: ModWidthSOF
7
6
5
4
3
2
1
0
ModWidthSOF
Access Rights
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Description of the bits Bit 7-0 Symbol ModWidthSOF Function This register defines the width of the modulation pulse for SOF Tmod = 2(ModWidth +1) / fc . Register setting:
I*CODE1 Standard Mode: 0x3F (Modulation width SOF: 9.44s). I*CODE1 Fast Mode: 0x73 (Modulation width SOF: 18.88s).
ISO 15693: 0x3F (Modulation width SOF: 9.44s).
36
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.3.8
PreSet17 Register Address: 0x17 7 0 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w Reset value: 00000000, 0x00 2 0 r/w 1 0 r/w 0 0 r/w
Name: PreSet17
Access Rights
r/w
Note: These values shall not be changed !
5.2.4 5.2.4.1
PAGE 3: RECEIVER AND DECODER CONTROL Page Register
Selects the register page. See 5.2.1.1 Page Register.
5.2.4.2
RxControl1 Register
controls receiver behaviour. Name: RxControl1 Address: 0x19 Reset value: 10001011, 0x8B
7 1 Access Rights r/w
6 0 r/w
5 0 r/w
4 0 r/w
3 1 r/w
2 0 r/w
1 Gain r/w
0
r/w
Description of the bits Bit 7-2 1-0 Symbol 100010 Gain These values shall not be changed This register defines the receivers signal voltage gain factor: 00: 27 dB 01: 30 dB 10: 38 dB 11: 42 dB Function
37
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.4.3
DecoderControl Register
controls decoder behaviour. Name: DecoderControl Address: 0x1A Reset value: 00000000, 0x00
7 0 Access Rights r/w
6 Rx Multiple r/w
5 ZeroAfter Coll r/w
4 RxFraming r/w
3
2 RxInvert r/w
1 0 r/w
0 0 r/w
r/w
Description of the bits Bit 7 6 5 4-3 Symbol 0 RxMultiple ZeroAfterColl RxFraming These values shall not be changed If set to 0, the receiver is deactivated after receiving the Datastream. If set to 1, it is possible to receive more than one Frame. If set to 1, any bits received after a bit-collision are masked to zero. This eases resolving the anti-collision procedure defined in the standard ISO 15693. Selects the receiving frame type 00 for I*CODE1 01 RFU 10 ISO 15693 11 RFU If set to 0, a modulation at the first half bit results a logic 1 (according I*CODE1) If set to 1, a modulation at the first half bit results a logic 0 (according ISO15693) These values shall not be changed Function
2 1-0
RxInvert 00
38
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.4.4
BitPhase Register
selects the bit-phase between transmitter and receiver clock. Name: BitPhase Address: 0x1B Reset value: 01010100, 0x54
7
6
5
4 BitPhase
3
2
1
0
Access Rights
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Description of the bits Bit 7-0 Symbol BitPase Function Defines the phase relation between transmitter and receiver clock. Note: The correct value of this register is essential for proper operation.
39
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.4.5
RxThreshold Register
selects thresholds for the bit decoder. Name: RxThreshold Address: 0x1C Reset value: 01101000, 0x68
7
6 MinLevel
5
4
3
2 CollLevel
1
0
Access Rights
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Description of the bits Bit 7-4 Symbol MinLevel Function Defines the minimum signal strength at the decoder input that shall be accepted. If the signal strength is below this level, it is not evaluated. 3-0 CollLevel Defines the minimum signal strength at the decoder input that has to be reached by the weaker half-bit of the Manchester-coded signal to generate a bit-collision relatively to the amplitude of the stronger half-bit.
5.2.4.6
PreSet1D Register Address: 0x1D Reset value: 00000000, 0x00
Name: PreSet1D
7 0 Access Rights r/w
6 0 r/w
5 0 r/w
4 0 r/w
3 0 r/w
2 0 r/w
1 0 r/w
0 0 r/w
Note: These values shall not be changed !
40
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.4.7
RxControl2 Register
controls decoder behaviour and defines the input source for the receiver. Name:RxControl2 Address: 0x1E Reset value: 01000001, 0x41
7 RcvClkSelI Access Rights R/w
6 RxAutoPD r/w
5 0 r/w
4 0 r/w
3 0 r/w
2 0 r/w
1
0
DecoderSource r/w r/w
Description of the bits Bit 7 Symbol RcvClkSelI Function If set to 1, the I-clock is used for the receiver clock. 0 indicates, the Q-clock is used. I-clock and Q-clock are 90 phase shifted to each other If set to 1, the receiver circuit is automatically switched on before receiving and switched off afterwards. This may be used to reduce current consumption. If set to 0, the receiver is always activated. 5-2 1-0 0000 DecoderSource These values shall not be changed Selects the source for the decoder input: 00: Low 01: Internal Demodulator 10: RFU 11: RFU
6
RxAutoPD
41
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.4.8
ClockQControl Register
controls clock generation for the 90 phase shifted Q-channel clock. Name: ClockQControl Address: 0x1F Reset value: 000XXXXX, 0xXX
7 ClkQ180Deg Access Rights r
6 ClkQCalib r/w
5 0 r/w
4
3
2 ClkQDelay
1
0
dy
dy
dy
dy
dy
Description of the bits Bit 7 6 Symbol ClkQ180Deg ClkQCalib Function If the Q-clock is phase shifted more than 180 compared to the I-clock, this bit is set to 1, otherwise it is 0. If this bit is 0, the Q-clock is calibrated automatically after the Reset Phase and after data reception from the label. If this bit is set to 1, no calibration is performed automatically. This value shall not be changed This register shows the number of delay elements actually used to generate a 90 phase shift of the I-clock to obtain the Q-clock. It can be written directly by the -Processor or by the automatic calibration cycle.
5 4-0
0 ClkQDelay
42
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.5 5.2.5.1
PAGE 4: RF-TIMING AND CHANNEL REDUNDANCY Page Register
Selects the register page. See 5.2.1.1 Page register.
5.2.5.2
RxWait Register
Selects the time interval after transmission, before receiver starts. Name: RxWait Address: 0x21 Reset value: 00001000, 0x08
7
6
5
4 RxWait
3
2
1
0
Access Rights
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Description of the bits Bit 7-0 Symbol RxWait Function After data transmission, the activation of the receiver is delayed for RxWait bitclocks (proportional to CoderRate). During this `frame guard time' any signal at pin Rx is ignored.
43
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.5.3
ChannelRedundancy Register
Selects kind and mode of checking the data integrity on the RF-channel. Name: ChannelRedundancy Address: 0x22 Reset value: 00001100, 0x0C
7 0 Access Rights r/w
6 CRCMSB First r/w
5 CRC 3309 r/w
4 CRC8 r/w
3 RxCRCEn r/w
2 TxCRCEn r/w
1 0 r/w
0 0 r/w
Description of the bits Bit 7 6 Symbol 0 CRCMSBFirst This value shall not be changed If set to 1, CRC-calculation shifts the MSBit into the CRC-Coprocessor first. If set to 0, CRC-calculation starts with the LSBit. Note: For usage according ISO 15693 and I?CODE1 this bit has to be 0. 5 CRC 3309 If set to 1, CRC-calculation is done according ISO/IEC3309 as it is defined in ISO 15693. Note: For usage according to I*CODE1 this bit has to be 0. 4 3 CRC8 RxCRCEn If set to 1, an 8-bit CRC is calculated. If set to 0, a 16-bit CRC is calculated. If set to 1, the last byte(s) of a received frame is/are interpreted as CRC byte/s. If the CRC itself is correct the CRC byte(s) is/are not passed to the FIFO. In case of an error, the CRCErr flag is set. If set to 0, no CRC is expected. If set to 1, a CRC is calculated over the transmitted data and the CRC byte(s) are appended to the data stream. If set to 0, no CRC is transmitted. RFU Function
2
TxCRCEn
1-0
00
44
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.5.4
CRCPresetLSB Register
LSB of the preset value for the CRC register. Name: CRCPresetLSB Address: 0x23 Reset value: 11111110, 0xFE
7
6
5
4
3
2
1
0
CRCPresetLSB Access Rights r/w r/w r/w r/w r/w r/w r/w r/w
Description of the bits Bit 7-0 Symbol CRCPresetLSB Function CRCPresetLSB defines the starting value for CRC-calculation. This value is loaded into the CRC at the beginning of transmission, reception and the CalcCRC Command, if the CRC calculation is enabled. The Preset value is set for I?CODE1 To use the ISO 15693 functionality the CRCPresetLSB Register has to be set to 0xFF.
5.2.5.5
CRCPresetMSB Register
MSB of the preset value for the CRC register. Name: CRCPresetMSB Address: 0x24 Reset value: 11111111, 0xFF
7
6
5
4
3
2
1
0
CRCPresetMSB Access Rights r/w r/w r/w r/w r/w r/w r/w r/w
Description of the bits Bit 7-0 Symbol CRCPresetMSB Function CRCPresetMSB defines the starting value for CRC-calculation. This value is loaded into the CRC at the beginning of transmission, reception and the CalcCRC Command, if the CRC calculation is enabled. Note: The Preset value of CRCPresetMSB Register is the same for I?CODE1 and ISO 15693. Note: This register is not relevant, if CRC8 is 1.
45
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.5.6
TimeSlotPeriod Register Address: 0x25 Reset value: 00000000, 0x00
Name: TimeSlotPeriod
7
6
5
4
3
2
1
0
TimeSlotPeriod Access Rights r/w r/w r/w r/w r/w r/w r/w r/w
Description of the bits Bit 7-0 Symbol
TimeSlotPeriod
Function TimeSlotPeriod defines the time between automatically mitted Frames. To send a Quit-Frame according to the I*CODE1 protocol, it is necessary to have a relation to the beginning of the Command-Frame. The TimeSlotPeriod will start at the End of the Command transmission. For detailed information see also chapter 9.2.5
46
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.5.7
SIGOUTSelect Register
Selects internal signal applied to pin SIGOUT.
Name: SIGOUTSelect
Address: 0x26
Reset value:00000000, 0x00
7 0
6 0
5 0
4 TimeSlot Period MSB r/w
3 0
2
1 SIGOUTSelect
0
Access Rights
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Description of the bits Bit 7-5 4 3 2-0 Symbol 000 TimeSlotPeriod MSB 0 SIGOUTSelect These values shall not be changed MSB of value TimeSlotPeriod see register 0x25 These values shall not be changed SIGOUTSelect defines which signal is routed to pin SIGOUT. Function
000 001 010 011 100 101 110 111
Constant Low Constant High Modulation Signal (envelope) from internal coder, actual used coded Serial data stream Output signal of the carrier frequency demodulator (label modulation signal) Output signal of the subcarrier demodulator (Manchester coded label signal) RFU RFU
47
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.5.8
PreSet27 Register Address: 0x27 Reset value: 00000000, 0x00
Name: PreSet27
7 0 Access Rights r/w
6 0 r/w
5 0 r/w
4 0 r/w
3 0 r/w
2 0 r/w
1 0 r/w
0 0 r/w
Note: These values shall not be changed !
5.2.6 5.2.6.1
PAGE 5: FIFO, TIMER AND IRQ- PIN CONFIGURATION Page Register
Selects the register page. See 5.2.1.1 Page register.
5.2.6.2
FIFOLevel Register
Defines the level for FIFO under- and overflow warning. Name: FIFOLevel Address: 0x29 Reset value:00111110, 0x3E
7 0 Access Rights r/w
6 0 r/w
5
4
3 WaterLevel
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
Description of the bits Bit 7-6 5-0 Symbol 00 WaterLevel These values shall not be changed This register defines, the warning level of the SL RC400 for the -Processor for a FIFO-buffer over- or underflow: HiAlert is set to 1, if the remaining FIFO-buffer space is equal or less than WaterLevel bytes in the FIFO-buffer. LoAlert is set to 1, if equal or less than WaterLevel bytes are in the FIFO-buffer,. Function
48
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.6.3
TimerClock Register
Selects the devider for the timer clock. Name: TimerClock Address: 0x2A Reset value: 00001011, 0x0B
7 0 Access Rights r/w
6 0 r/w
5 TAutoRestart r/w
4
3
2 TPreScaler
1
0
r/w
r/w
r/w
r/w
r/w
Description of the bits Bit 7-6 5 Symbol 00 TAutoRestart These values shall not be changed If set to 1, the timer automatically restart its count-down from TReloadValue, instead of counting down to zero. If set to 0 the timer decrements to zero and the bit TimerIRq is set to 1. Defines the timer clock fTimer. TPreScaler can be adjusted from 0x00 up to 0x15. The following formula is used to calculate fTimer : fTimer = 13.56 MHz / 2
TPreScaler
Function
4-0
TPreScaler
.
49
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.6.4
TimerControl Register
Selects start and stop conditions for the timer. Name: TimerControl Address: 0x2B Reset value: 00000010, 0x02
7 0 Access Rights r/w
6 0 r/w
5 0 r/w
4 0 r/w
3 TStopRxEnd r/w
2 TStopRxBegin r/w
1 TStartTxEnd r/w
0 TStartTxBegin r/w
Description of the bits Bit 7-4 3 2 1 Symbol 0000 TStopRxEnd TStopRxBegin TStartTxEnd These values shall not be changed If set to 1, the timer is stopped automatically when data reception ends. 0 indicates, that the timer is not influenced by this condition. If set to 1, the timer is stopped automatically, when the first valid bit is received. 0 indicates, that the timer is not influenced by this condition. If set to 1, the timer is started automatically when data transmission ends. If the timer is already running, it is restarted by loading TReloadValue into the timer. 0 indicates, that the timer is not influenced by this condition. If set to 1, the timer is started automatically when the first bit is transmitted. If the timer is already running, it is restarted by loading TReloadValue into the timer. 0 indicates, that the timer is not influenced by this condition. Function
0
TStartTxBegin
50
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.6.5
TimerReload Register
Defines the preset value for the timer. Name: TimerReload Address: 0x2C Reset value: 00000000, 0x00
7
6
5
4
3
2
1
0
TReloadValue Access Rights r/w r/w r/w r/w r/w r/w r/w r/w
Description of the bits Bit 7-0 Symbol TReloadValue Function With a start event the timer loads with the TreloadValue. Changing this register affects the timer only with the next start event. If TReloadValue is set to 0, the timer cannot start.
51
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.6.6
IRQPinConfig Register
Configures the output stage for pin IRQ. Name: IRQPinConfig Address: 0x2D Reset value: 00000010, 0x02
7 0 Access Rights r/w
6 0 r/w
5 0 r/w
4 0 r/w
3 0 r/w
2 0 r/w
1 IRQInv r/w
0 IRQPushPull r/w
Description of the bits Bit 7-2 1 0 Symbol 000000 IRQInv IRQPushPull These values shall not be changed If set to 1, the signal on pin IRQ is inverted with respect to bit IRq. 0 indicates, that the signal on pin IRQ is equal to bit IRQ. If set to 1, pin IRQ works as standard CMOS output pad. 0 indicates, that pin IRQ works as open drain output pad. Function
5.2.6.7
PreSet2E Address: 0x2E Reset value: 00000000, 0x00
Name: PreSet2E
7 0 Access Rights r/w
6 0 r/w
5 0 r/w
4 0 r/w
3 0 r/w
2 0 r/w
1 0 r/w
0 0 r/w
Note: These values shall not be changed !
5.2.6.8
Preset2F Address: 0x2F Reset value: 00000000, 0x00
Name: Preset2F
7 0 Access Rights r/w
6 0 r/w
5 0 r/w
4 0 r/w
3 0 r/w
2 0 r/w
1 0 r/w
0 0 r/w
Note: These values shall not be changed !
52
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
Page 6: RFU 5.2.6.9 Page Register
Selects the register page. See 5.2.1.1 Page register.
5.2.6.10 RFU Registers
Name: RFU
Address: 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 037
Reset value:00000000, 0x00
7 0 Access Rights r/w
6 0 r/w
5 0 r/w
4 0 r/w
3 0 r/w
2 0 r/w
1 0 r/w
0 0 r/w
Note: These registers are reserved for future use.
53
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.7 5.2.7.1
PAGE 7: TEST CONTROL Page Register
Selects the register page. See 5.2.1.1 Page register.
5.2.7.2
RFU Register Address: 0x39 Reset value: 00000000, 0x00
Name: RFU
7 0
6 0
5 0
4 0 w
3 0 w
2 0 w
1 0 w
0 0 w
Access w w w Rights Note: These registers are reserved for future use.
54
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.7.3
TestAnaSelect Register
Selects analog test signals. Name: TestAnaSelect Address: 0x3A Reset value: 00000000, 0x00
7 0 Access Rights w
6 0 w
5 0 w
4 0 w
3
2
1
0
TestAnaOutSelect w w w w
Description of the bits Bit 7-4 3-0 Symbol 0000 TestAnaOutSel These values shall not be changed This register selects the internal analog signal that is routed to pin AUX. For detailed information see 18.3 Value 0 1 2 3 4 5 6 7 8 9 A B C D E F Signal Name Vmid Vbandgap VRxFollI VRxFollQ VRxAmpI VRxAmpQ VCorrNI VCorrNQ VCorrDI VCorrDQ VEvalL VEvalR VTemp RFU RFU RFU Function
55
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.7.4
PreSet3B Address: 0x3B Reset value: 00000000, 0x00
Name: PreSet3B
7 0 Access Rights w
6 0 w
5 0 w
4 0 w
3 0 w
2 0 w
1 0 w
0 0 w
Note: These values shall not be changed !
5.2.7.5
PreSet3C Address: 0x3C Reset value: 00000000, 0x00
Name: PreSet3C
7 0 Access Rights w
6 0 w
5 0 w
4 0 w
3 0 w
2 0 w
1 0 w
0 0 w
Note: These values shall not be changed !
56
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.2.7.6
TestDigiSelect Register
Selects digital test mode. Name: TestDigiSelect Address:0x3D Reset value: 00000000, 0x00
7 SignalTo SIGOUT Access Rights w
6
5
4
3 TestDigiSignalSel
2
1
0
w
w
w
w
w
w
w
Description of the bits Bit 7 Symbol SignalToSIGOUT Function Set to 1, overrules the setting in SIGOUTSelect and the digital test signal defined in TestDigiSignalSel is routed to pin SIGOUT instead. Set to 0, SIGOUTSelect defines the signal delivered at pin SIGOUT. Selects the digital test signal to be routed to pin SIGOUT. For detailed information refer to chapter 18.4 TestDigiSelect 74hex 64hex 54hex 44hex 35hex 25hex 16hex Signal Name s_data s_valid s_coll s_clock rd_sync wr_sync int_clock
6-0
TestDigiSignalSel
5.2.7.7
RFU Registers Address: 0x3E, 0x3F Reset value: 00000000, 0x00
Name: RFU
7 0
6 0
5 0
4 0 r/w
3 0 r/w
2 0 r/w
1 0 r/w
0 0 r/w
Access r/w r/w r/w Rights Note: These registers are reserved for future use.
57
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.3
SL RC400 Register Flags Overview Register ErrorFlag BitPhase ClockQControl ClockQControl ClockQControl ErrorFlag RxThreshold CollPos Command ChannelRedundancy ChannelRedundancy ErrorFlag ChannelRedundancy CRCPresetLSB CRCPresetMSB SecondaryStatus CRCResultMSB CRCResultLSB RxControl2 SecondaryStatus PrimaryStatus FIFOData FIFOLength ErrorFlag Control ErrorFlag RxControl1 CWConductance ModConductance PrimaryStatus InterruptEn InterruptRq Address Register, Bit Position 0x0A, bit 5 0x1B, bits 7:0 0x1F, bit 7 0x1F, bit 6 0x1F, bits 4:0 0x0A, bit 0 0x1C, bits 3:0 0x0B, bits 7:0 0x01, bits 5:0 0x22, bit 5 0x22, bit 4 0x0A, bit 3 0x22, bit 6 0x23, bits 7:0 0x24, bits 7:0 0x05 , bit 5 0x0E, bits 7:0 0x0D, , bits 7:0 0x1E, bits 1:0 0x05, bit 6 0x03, bit 2 0x02, bits 7:0 0x04, bits 7:0 0x0A, bit 4 0x09, bit 0 0x0A, bit 2 0x19, bits 1:0 0x12, bits 5:0 0x13, bits 5:0 0x03, bit 1 0x06, bit 1 0x07, bit 1 58 Preliminary
Flag(s) AccessErr BitPhase ClkQ180Deg ClkQCalib ClkQDelay CollErr CollLevel CollPos Command CRC3309 CRC8 CRCErr CRCMSBFirst CRCPresetLSB CRCPresetMSB CRCReady CRCResultMSB CRCResultLSB DecoderSource E2Ready Err FIFOData FIFOLength FIFOOvfl FlushFIFO FramingErr Gain GsCfgCW GsCfgMod HiAlert HiAlertIEn HiAlertIRq
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
Flag(s) IdleIEn IdleIRq IFDetectBusy IRq IRQInv IRQPushPull LoAlert LoAlertIEn LoAlertIRq SIGOUTSelect MinLevel ModemState ModulatorSource ModWidth PageSelect PowerDown RcvClkSelI RxAutoPD RxCRCEn RxIEn RxIRq RxLastBits RxWait SetIEn SetIRq SignalToSIGOUT StandBy TAutoRestart TestAnaOutSel TestDigiSignalSel TimerIEn TimerIRq TimerValue
Register InterruptEn InterruptRq Command PrimaryStatus IRQPinConfig IRQPinConfig PrimaryStatus InterruptEn InterruptRq SIGOUTSelect RxThreshold PrimaryStatus TxControl ModWidth Page Control RxControl2 RxControl2 ChannelRedundancy InterruptEn InterruptRq SecondaryStatus RxWait InterruptEn InterruptRq TestDigiSelect Control TimerClock TestAnaSelect TestDigiSelect InterruptEn InterruptRq TimerValue
Address Register, Bit Position 0x06, bit 2 0x07, bit 2 0x01, bit 7 0x03, bit 3 0x2D, bit 1 0x2D, bit 0 0x03, bit 0 0x06, bit 0 0x07, bit 0 0x26, bits 2:0 0x1C, bits 7:4 0x03 , bit 6:4 0x11, bits 6:5 0x15, bits /:0 0x00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30, 0x38, bits 2:0 0x09, bit4 0x1E, bit 7 0x1E, bit 6 0x22, bit 3 0x06, bit 3 0x07, bit 3 0x05, bits 2:0 0x21, bits 7:0 0x06, bit 67 0x07, bit 7 0x3D, bit 7 0x09, bit 5 0x2A, bit 5 0x3A, bits 6:4 0x3D, bit 6:0 0x06, bit 5 0x07, bit 5 0x0C, bits 7:0 59 Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
Flag(s) TPreScaler TReloadValue TRunning TStartTxBegin TStartTxEnd TStartNow TStopRxBegin TStopRxEnd TStopNow TX1RFEn TX2Cw TX2Inv TX2RFEn TxCRCEn TxIEn TxIRq TxLastBits UsePageSelect WaterLevel ZeroAfterColl
Register TimerClock TimerReload SecondaryStatus TimerControl TimerControl Control TimerControl TimerControl Control TxControl TxControl TxControl TxControl ChannelRedundancy InterruptEn InterruptRq BitFraming Page FIFOLevel DecoderControl
Address Register, Bit Position 0x2A, bits 4:0 0x2C, bits 7:0 0x05, bit 7 0x2B, bit 0 0x2B, bit 1 0x09, bit 1 0x2B, bit 2 0x2B, bit 3 0x09, bit 2 0x11, bit 0 0x11, bit 3 0x11, bit 3 0x11, bit 1 0x22, bit 2 0x06, bit 4 0x07, bit 4 0x0F, bits 2:0 0x00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30, 0x38, bit 7 0x29, bits 5:0 0x1A, bit 5
60
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
5.4
Modes of Register Addressing
There are three mechanisms to operate the SL RC400: * * * Initiating functions and controlling data manipulation by executing commands Configuring electrical and functional behaviour via a set of configuration bits Monitoring the state of the SL RC400 by reading status flags
The commands, configurations bits and flags are accessed via the -Processor interface. The SL RC400 can internally address 64 registers. This basically requires six address lines.
5.4.1
PAGING MECHANISM
The SL RC400 register set is segmented into 8 pages with 8 register each. The Page-Register can always be addressed, no matter which page is currently selected.
5.4.2
DEDICATED ADDRESS BUS
Using the SL RC400 with dedicated address bus, the -Processor defines three address lines via the address pins A0, A1, and A2. This allows addressing within a page. To switch between registers in different pages the paging mechanism needs then to be used. The following table shows how the register address is assembled:
Register Bit: UsePageSelect Register-Address
1
PageSelect2
PageSelect1
PageSelect0
A2
A1
A0
Table 5-3: Dedicated Address Bus: Assembling the Register Address
5.4.3
MULTIPLEXED ADDRESS BUS
Using the SL RC400 with multiplexed address bus, the -Processor may define all six address lines at once. In this case either the paging mechanism or linear addressing may be used. The following table shows how the register address is assembled:
Interface Bus Type Multiplexed Address Bus (paging mode) Multiplexed Address Bus (linear addressing) Register Bit: UsePageSelect Register-Address
1 0
PageSelect2 AD5
PageSelect1 AD4
PageSelect0 AD3
AD2 AD2
AD1 AD1
AD0 AD0
Table 5-4: Multiplexed Address Bus: Assembling the Register Address
61
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
6 6.1
MEMORY ORGANISATION OF THE EPROM Diagram of the EPROM Memory Organisation
Block Address 0 1 2 3 4 5 6 7 Byte Addresses 00 ... 0F 10 ... 1F 20 ... 2F 30 ... 3F 40 ... 4F 50 ... 5F 60 ... 6F 70 ... 7F Access Rights r r/w r/w r/w r/w r/w r/w r/w Register Initialisation File For User data or second Initialisation Memory Content Product Information Field Start Up Register Initialisation File See Also 6.2 6.3.1
Block Number 0 1 2 3 4 5 6 7
6.3.3
Table 6-1:Diagram of EPROM Memory Organisation Note: It is strictly recommended to use only the described EPROM address area.
6.2
Product Information Field (Read Only)
0 1 2 3 4 5 6 RFU 7 8 9 10 11 12 Internal 13 14 RsMaxP 15 CRC
Byte Meaning
Product Type Identification
Product Serial Number
Table 6-2: Product Information Field
PRODUCT TYPE IDENTIFICATION The SL RC400 is a member of a new family for highly integrated reader IC's. Each member of the product family has its unique Product Type Identification. The value of the Product Type Identification is shown in the table below:
Product Type Identification Byte Value 0 30hex 1 33hex 2 F1 hex 3 00hex 4 XXhex
Table 6-3: Product Type Identification Definition
62
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
PRODUCT SERIAL NUMBER The SL RC400 holds a four byte serial number that is unique for each device. INTERNAL: These 2 bytes hold internal trimming parameters. MAXIMUM SOURCE RESISTANCE FOR THE P-CHANNEL DRIVER TRANSISTOR OF PIN TX1 AND TX2 The source resistance of the p-channel driver transistors of pin TX1 and TX2 may be adjusted via the GsConfCW Register (see chapter 13.2.1). The mean value of the maximum adjustable source resistance of the pins TX1 and TX2 is stored as an integer value in Ohms in byte RsMaxP. This value is denoted as maximum adjustable source resistance Rs ref,max,n and is measured with GsConfCW Register set to 01hex . It is in the range between about 80 to 120 O. CRC The content of the product information field is secured via a CRC-byte, which is checked during start up.
6.3
Register Initialisation Files (Read/Write)
Register initialisation in the register address range from 10hex to 2Fhex is done automatically during the Initialising Phase (see 11.3), using the Start Up Register Initialisation File. Furthermore, the user may initialise the SL RC400 registers with values from the Register Initialisation File executing the LoadConfig-Command (see 16.6.1). Notes: * * * The Page-Register (addressed with 10hex , 18hex , 20hex , 28hex ) is skipped and not initialised. Make sure that all PreSet registers are not changed. Make sure, that all register bits that are reserved for future use (RFU) are set to 0.
6.3.1
START UP REGISTER INITIALISATION FILE (READ/WRITE)
The content of the EPROM memory block address 1 and 2 are used to initialise the SL RC400 registers 10hex to 2Fhex during the Initialising Phase automatically. The default values written into the EPROM during production are shown in chapter 6.3.2. The assignment is the following:
EPROM Byte Address 10hex (Block 1, Byte 0) 11hex ... 2Fhex (Block 2, Byte 15) Register Address 10hex 11hex ... 2Fhex Remark Skipped Copied ... Copied
Table 6-4: Byte Assignment for Register Initialisation at Start Up
63
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
6.3.2
SHIPMENT CONTENT OF START UP REGISTER INITIALISATION FILE
During production test, the Start Up Register Initialisation File is initialised with the values shown in the table below. With each power up these values are written into the SL RC400 register during the Initialising Phase.
EPROM Byte Address 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F Reg. Address 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F Value 00 58 3F 05 2C 3F 3F 00 00 8B 00 54 68 00 41 00 00 08 0C FE FF 00 00 00 00 3E 0B 02 00 02 00 00 Page: free for user TxControl: Transmitter pins TX1 and TX2 switched off, bridge driver configuration, modulator driven from internal digital circuitry CwConductance: Source resistance of TX1 and TX2 to minimum. ModGsCfg: Source resistance of TX1 and TX2 at the time of Modulation, to determine the modulation index CoderControl: Selects the bit coding mode and the framing during transmission ModWidth: Pulse width for "used code (1 out of 256, RZ or 1 out of 4)" pulse coding is set to standard configuration. ModWidthSOF Pulse width of SOF PreSet17 Page: free for user RxControl1: Amplifier gain is maximum. DecoderControl: A bit-collision always evaluates to HIGH in the data bit stream. BitPhase: BitPhase is set to standard configuration. RxThreshold: MinLevel and CollLevel are set to maximum. PreSet1D RxControl2: Use Q-clock for the receiver, `Automatic Receiver Off' is switched on, decoder is driven from internal analog circuitry. ClockQControl: Automatic Q-clock Calibration' is switched on. Page: free for user RxWait: Frame Guard Time is set to six bit clocks. ChannelRedundancy: Channel Redundancy is set according to I?CODE1. CRCPresetLSB: CRC-Preset value is set according to I?CODE1. CRCPresetMSB: CRC-Preset value is set according to I?CODE1. PreSet25 SIGOUTSelect: Pin SIGOUT is set to LOW. PreSet27 Page: free for user FIFOLevel: WaterLevel: FIFO buffer warning level is set to standard configuration. TimerClock: TPreScaler is set to standard configuration, timer unit restart function is switched off. TimerControl: Timer is started at the end of transmission, stopped at the beginning of reception. TimerReload: TReloadValue: the timer unit preset value is set to standard configuration IRQPinConfig: Pin IRQ is set to high impedance. PreSet2E PreSet2F Description
Table 6-5: Shipment Content of Start Up Configuration File 64 Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
6.3.3
REGISTER INITIALISATION FILE (READ/WRITE)
The content of the EPROM memory from block address 3 to 7 may be used to initialise the SL RC400 registers 10hex to 2Fhex by execution of the LoadConfig-Command (see 16.6.1). It requires a two byte argument, that is used as the two byte long EPROM starting byte address for the initialisation procedure. The assignment is the following:
EPROM Byte Address Starting Byte address for the EPROM Starting Byte address for the EPROM +1 ... Starting Byte address for the EPROM + 31 Register Address 10hex 11hex ... 2Fhex Remark Skipped Copied ... Copied
Table 6-6: Byte Assignment for Register Initialisation at Start Up
The Register Initialisation File is big enough to hold the values for two initialisation sets and leaves one more block (16 bytes) for the user. Note: The Register Initialisation File is read- and write-able for the user. Therefore, these bytes may also be used to store user specific data for other purposes.
65
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
7 7.1
FIFO BUFFER Overview
An 8x64 bit FIFO buffer is implemented in the SL RC400 acting as a parallel-to-parallel converter. It buffers the input and output data stream between the -Processor and the internals of the SL RC400. Thus, it is possible to handle data streams with lengths of up to 64 bytes without taking timing constraints into account.
7.2 7.2.1
Accessing the FIFO Buffer ACCESS RULES
The FIFO-buffer input and output data bus is connected to the FIFOData Register. Writing to this register stores one byte in the FIFO-buffer and increments the internal FIFO-buffer write-pointer. Reading from this register shows the FIFO-buffer content stored at the FIFO-buffer read-pointer and increments the FIFObuffer read-pointer. The distance between the write- and read-pointer can be obtained by reading the FIFOLength Register. When the -Processor starts a command, the SL RC400 may, while the command is in progress, access the FIFO-buffer according to that command. Physically only one FIFO-buffer is implemented, which can be used in input- and output direction. Therefore the -Processor has to take care, not to access the FIFO-buffer in an unintended way. The following table gives an overview on FIFO access during command processing:
Active Command StartUp Idle Transmit Receive Transceive WriteE2 ReadE2 LoadConfig CalcCRC -Processor is allowed to Write to FIFO u u u u u u Read from FIFO u u u The -Processor has to prepare the arguments, then only reading is allowed -Processor has to know the actual state of the command (transmitting or receiving) Remark
Table 7-1: Allowed Access to the FIFO-Buffer
7.3
Controlling the FIFO-Buffer
Besides writing and reading the FIFO-buffer, the FIFO-buffer pointers may be reset by setting the bit FlushFIFO. The consequence is, that FIFOLength becomes zero, FIFOOvfl is cleared, the actually stored bytes are not accessible anymore and the FIFO-buffer can be filled with another 64 bytes again.
66
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
7.4
Status Information about the FIFO-Buffer
The -Processor may obtain the following data about the FIFO-buffers status: * * * * Number of bytes already stored in the FIFO-buffer: FIFOLength Warning, that the FIFO-buffer is quite full: HiAlert Warning, that the FIFO-buffer is quite empty: LoAlert Indication, that bytes were written to the FIFO-buffer although it was already full: FIFOOvfl FIFOOvfl can be cleared only by setting bit FlushFIFO.
The SL RC400 can generate an interrupt signal * If LoAlertIRq is set to 1 it will activate Pin IRQ when LoAlert changes to 1. * If HiAlertIRq is set to 1 it will activate Pin IRQ when HiAlert changes to 1. The flag HiAlert is set to 1 if only WaterLevel bytes or less can be stored in the FIFO-buffer. It is generated by the following equation:
HiAlert = (64 - FIFOLength) WaterLevel
The flag LoAlert is set to 1 if WaterLevel bytes or less are actually stored in the FIFO-buffer. It is generated by the following equation:
LoAlert = FIFOLength WaterLevel
67
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
7.5
Register overview FIFO Buffer
The following table shows the related flags of the FIFO buffer in alphabetic order.
Flags FIFOLength FIFOOvfl FlushFIFO HiAlert HiAlertIEn HiAlertIRq LoAlert LoAlertIEn LoAlertIRq WaterLevel
Register FIFOLength ErrorFlag Control PrimaryStatus InterruptIEn InterruptIRq PrimaryStatus InterruptIEn InterruptIRq FIFOLevel
Address Register, bit position 0x04, bits 6-0 0x0A, bit 4 0x09, bit 0 0x03, bit 1 0x06, bit 1 0x07, bit 1 0x03, bit 0 0x06, bit 0 0x07, bit 0 0x29, bits 5-0
Table 7-2. Registers associated with the FIFO Buffer
68
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
8 8.1
INTERRUPT REQUEST SYSTEM Overview
The SL RC400 indicates certain events by setting bit IRq in the PrimaryStatus-Register and, in addition, by activating pin IRQ. The signal on pin IRQ may be used to interrupt the -Processor using its interrupt handling capabilities. This allows the implementation of efficient -Processor software.
8.1.1
INTERRUPT SOURCES OVERVIEW
The following table shows the integrated interrupt flags, the related source and the condition for its setting. The interrupt flag TimerIRq indicates an interrupt set by the timer unit. The setting is done when the timer decrements from 1 either down to zero (TAutoRestart flag disabled) or to the TPreLoad value if TAutoRestart is enabled. The TxIRq bit indicates interrupts from different sources. If the transmitter is active and the state changes from sending data to transmitting the end of frame pattern, the transmitter unit sets automatically the interrupt bit. The CRC coprocessor sets TxIRq after having processed all data from the FIFO buffer. This is indicated 2 by the flag CRCReady = 1. If the E Prom programming has finished the TxIRq bit is set, indicated by the bit E2Ready = 1. The RxIRq flag indicates an interrupt when the end of the received data is detected. The flag IdleIRq is set if a command finishes and the content of the command register changes to idle. The flag HiAlertIRq is set to 1 if the HiAlert bit is set to one, that means the FIFO buffer has reached the level indicated by the bit WaterLevel, see chapter 7.4. The flag LoAlertIRq is set to 1 if the LoAlert bit is set to one, that means the FIFO buffer has reached the level indicated by the bit WaterLevel, see chapter 7.4.
Interrupt Flag TimerIRq TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq
Interrupt Source Timer Unit Transmitter CRC-Coprocessor Receiver Command Register FIFO-buffer FIFO-buffer
Is set automatically, when the timer counts from 1 to 0 a data stream, transmitted to the label, ends all data from the FIFO buffer has been processed a data stream, received from the label, ends a command execution finishes the FIFO-buffer is getting full the FIFO-buffer is getting empty
Table 8-1: Interrupt Sources
69
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
8.2 8.2.1
Implementation of Interrupt Request Handling CONTROLLING INTERRUPTS AND THEIR STATUS
The SL RC400 informs the -Processor about the interrupt request source by setting the according bit in the InterruptRq Register. The relevance of each interrupt request bit as source for an interrupt may be masked with the interrupt enable bits of the InterruptEn Register.
Register InterruptEn InterruptRq Bit 7 SetIEn SetIRq Bit 6 RFU RFU Bit 5 TimerIEn TimerIRq Bit 4 TxIEn TxIRq Bit 3 RxIEn RxIRq Bit 2 IdleIEn IdleIRq Bit 1 HiAlertIEn HiAlertIRq Bit 0 LoAlertIEn LoAlertIRq
Table 8-2: Interrupt Control Registers If any interrupt request flag is set to 1 (showing that an interrupt request is pending) and the corresponding interrupt enable flag is set the status flag IRq in the PrimaryStatus Register is set to 1. Furthermore, different interrupt sources can be set active simultaneously. Therefore, all interrupt request bits are `OR'ed and connected to the flag IRq and forwarded to pin IRQ.
8.2.2
ACCESSING THE INTERRUPT REGISTERS
The interrupt request bits are set automatically by the internal state machines of the SL RC400. Additionally the -Processor has access in order to set or to clear them. A special implementation of the InterruptRq and the InterruptEn Register allows to change the status of a single bit without influencing the other ones. If a specific interrupt register shall be set to one, the bit SetIxx has to be set to 1 and simultaneously the specific bit has to be set to 1 too. Vice versa, if a specific interrupt flag shall be cleared, a zero has to be written to the SetIxx and simultaneously the specific address of the interrupt register has to be set to 1. If a bit content shall not be changed during the setting or clearing phase a zero has to be written to the specific bit location. Example: writing 3Fhex to the InterruptRq Register clears all bits as SetIRq in this case is set to 0 and all other bits are set to 1. Writing 81hex sets bit LoAlertIRq to 1 and leaves all other bits untouched.
8.3
Configuration of Pin IRQ
The logic level of the status flag IRq is visible at pin IRQ. In addition, the signal on pin IRQ may be controlled by the following bits of the IRQPinConfig Register: * * IRQInv: if set to 0, the signal on pin IRQ is equal to the logic level of bit IRq. If set to 1, the signal on pin IRQ is inverted with respect to bit IRq.
IRQPushPull: if set to 1, pin IRQ has standard CMOS output characteristics otherwise it is an open drain output and an external resistor is necessary to achieve a HIGH level at this pin. Note: During the Reset Phase (see 11.2) IRQInv is set 1 and IRQPushPull to 0. This results in a high impedance at pin IRQ.
70
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
8.4
Register Overview Interrupt Request System
The following table shows the related flags of the Interrupt Request System in alphabetic order.
Flags HiAlertIEn HiAlertIRq IdleIEn IdleIRq IRq IRQInv IRQPushPull LoAlertIEn LoAlertIRq RxIEn RxIRq SetIEn SetIRq TimerIEn TimerIRq TxIEn TxIRq
Register InterruptEn InterruptRq InterruptEn InterruptRq PrimaryStatus IRQPinConfig IRQPinConfig InterruptEn InterruptRq InterruptEn InterruptRq InterruptEn InterruptRq InterruptEn InterruptRq InterruptEn InterruptRq
Address Register, bit position 0x06, bit 1 0x07, bit 1 0x06, bit 2 0x07, bit 2 0x03, bit 3 0x07, bit 1 0x07, bit 0 0x06, bit 0 0x07, bit 0 0x06, bit 3 0x07, bit 3 0x06, bit 7 0x07, bit 7 0x06, bit 5 0x07, bit 5 0x06, bit 4 0x07, bit 4
Table 8-3 Registers associated with the Interrupt Request System
71
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
9 9.1
TIMER UNIT Overview
A timer is implemented in the SL RC400. It derives its clock from the 13.56 MHz chip-clock. The -Processor may use this timer to manage timing relevant tasks. The timer unit may be used in one of the following configurations: * * * * * Timeout-Counter Watch-Dog Counter Stop Watch Programmable One-Shot Periodical Trigger
The timer unit can be used to measure the time interval between two events or to indicate that a specific event occurred after a specific time. The timer can be triggered by events which will be explained in the following, but the timer itself does not influence any internal event. A timeout during data receiving does not influence the receiving process automatically. Furthermore, several timer related flags are set and these flags can be used to generate an interrupt.
72
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
9.2 9.2.1
Implementation of the Timer Unit BLOCK DIAGRAM
The following block diagram shows the timer module.
TStartTxBegin TxBegin Event TStartTxEnd TxEnd Event TAutoRestart TStartNow
QS
TReloadValue [7:0]
parallel in start counter / parallel load
TRunning TStopNow
Q
R
stop counter RxEnd Event TStopRxEnd RxBegin Event TStopRxBegin Counter Module (x <= x-1)
TPreScaler [4:0]
13.56 MHz
Clock Divider
>clock parallel out
to Parallel Interface
TimerValue [7:0]
Counter = 0 ?
to Interrupt Logic: TimerIRq
Figure 9-1: Timer Module Block Diagram
The timer unit is designed in a way, that several events in combination with enabling flags start or stop the counter. For example, setting the bit TstartTxEnd to 1 enables to control the receiving of data using the timer unit. In addition the first received bit is indicated by TxEndEvent. This combination starts the counter at the defined TReloadValue. The timer stops either automatically if the counter value is equal to zero, or if a defined stop event happens (TautoRestart not enabled).
73
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
9.2.2
CONTROLLING THE TIMER UNIT
The main part of the timer unit is a down-counter. As long as the down-counter value is unequal zero, it decrements its value with each timer clock. If TAutoRestart is enabled the timer does not decrement down to zero. Having reached the value 1 the timer reloads with the next clock with the TimerReload value. The timer is started by loading a value from the TimerReload Register into the counter module. This may be triggered by one of the following events: * * * * Transmission of the first bit to the label (TxBegin Event) and bit TStartTxBegin is 1 Transmission of the last bit to the label (TxEnd Event) and bit TStartTxEnd is 1 The counter module decrements down to zero and bit TAutoRestart is 1 Bit TStartNow is set to 1 (by the -Processor)
Note: Every start-event re-loads the timer from the TimerReload Register. Thus, the timer unit is re-triggered. The timer can be configured to stop with one of the following events: * * * * Reception of the first valid bit from the label (RxBegin Event)and bit TStopRxBegin is set to 1 Reception of the last bit from the label (RxEnd event) and bit TStopRxEnd is set to 1 The counter module has decremented down to zero and bit TAutoRestart is set to 0 Bit TStopNow is set to 1 (by the -Processor)
Loading a new value, e.g. zero, into the TimerReload Register does not immediately influence the counter, since the TimerReload Register affects the counter units content only with the next start-event. Thus, the TimerReload Register may be changed even if the timer unit is already counting. The consequence of changing the TimerReload Register will be visible after the next start-event. If the counter is stopped by setting bit TStopNow, no TimerIRq is signalled.
9.2.3
TIMER UNIT CLOCK AND PERIOD
The clock of the timer unit is derived from the 13.56 MHz chip clock via a programmable divider. The clock selection is done with the TPreScaler Register, that defines the timer unit clock frequency according to the following formula:
TTimerClock =
1 f TimerClock
=
2T PreScaler 13.56MHz
The possible values for the TPreScaler Register range from 0 up to 21. This results in minimum time TTimerClock of about 74 ns up to about 150 ms. The time period elapsed since the last start event is calculated with
TTimer =
TReLoadVal ue - TimerValue f TimerClock
This results in a minimum time TTimer of about 74 ns up to about 40 s.
74
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
9.2.4
STATUS OF THE TIMER UNIT
The TRunning bit in the SecondaryStatus Register shows the timer's current status. Any configured start event starts the timer at the TReloadValue and changes the status flag TRunning to 1, any configured stop event stops the timer and sets the status flag TRunning back to 0. As long as status flag TRunning is set to 1, the TimerValue Register changes with the next timer unit clock. The actual timer unit content can be read on-the-fly via the TimerValue Register.
9.2.5
TIMESLOTPERIOD
For sending of I*CODE1-Quit-Frames it is necessary to generat a exact chronological relation to the begin of the command frame. Is TimeSlotPeriod > 0, with the end of command transmission the TimeSlotPeriod starst. If there are Data in the FIFO after reaching the end of TimeSlotPeriod, these data were sent at that moment. If the FIFO is empty nothing happens. As long as the contend of TimeSlotPeriod is > 0 the counter for the TimeSlotPeriod will start automatically after reaching the end. This allows a exact time relation to the end (as well as to the beginning) of the command frame for the generation and sending of the I*CODE1-Quit-Frames Is TimeSlotPeriod > 0 the next Frame starts exact with the interval TimeSlotPeriod/CoderRate delayed after each previous Send Frame. CoderRate (see 5.2.3.5) defines the clock frequency of the coder. If TimeSlotPeriod = 0, the send function will not be triggered automatically. The contend of the register TimeSlotPeriod can be changed during the active mode. The modification take effect at the next restart of the TimeSlotPeriod.
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Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
Example: CoderRate = 0x05 (~52.97kHz) For I*CODE1 standard mode the interval should be 8.458ms ->TimeSlotPeriod = CoderRate * interval = 52.97kHz * 8.458ms -1 = 447 (447 = 0x1BF) Note: The MSB of the TimeSlotPeriod is in the SIGOUTSelect register see 5.2.5.7
Command
Quit1
Quit2
Response1
Response2
TSP1
TSP2
TimeSlotPeriod for TSP1 I*CODE1 Standard Mode I*CODE1 Fast Mode 0xBF 0x5F
TimeSlotPeriod for TSP2 0x1BF 0x67
Note: The MSB of the TimeSlotPeriod is in the SIGOUTSelect register see 5.2.5.7
Note: It is strictly recommended that bit TxCRCEn is set to 0 (see 5.2.5.3) before the Quit-Frame is sent. If the TxCRCEn is not set to 0 a CRC value is calculated and sent with the Quit-Frame. To calculate the Quit value a CRC8 algorithm has to be used.
76
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
9.3 9.3.1
Usage of the Timer Unit TIME-OUT- AND WATCH-DOG-COUNTER
Having started the timer by setting TReloadValue the timer unit decrements the TimerValue Register beginning with a certain start event. If a certain stop event occurs e.g. a bit is received from the label, the timer unit stops (no interrupt is generated). On the other hand, if no stop event occurs, e.g. the label does not answer in the expected time, the timer unit decrements down to zero and generates a timer interrupt request. This signals indicate the -Processor that the expected event has not occurred in the given time TTimer.
9.3.2
STOP WATCH
The time TTimer between a certain start- and stop event may be measured by the -Processor by means of the SL RC400 timer unit. Setting TReloadValue the timer starts to decrement. If the defined stop event occurs the timers stops. The time between start and stop can be calculated by
T = (T Re load
if the timer does not decrements down to zero.
value
- Timervalue ) * TTimer
9.3.3
PROGRAMMABLE ONE-SHOT TIMER
The -Processor starts the timer unit and waits for the timer interrupt. After the specified time TTimer the interrupt will occur (TautoRestart = 0).
9.3.4
PERIODICAL TRIGGER
If the -Processor sets bit TautoRestart and TreloadValue not equal 0, it will generate an interrupt request periodically after every TTimer.
77
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
9.4
Register Overview Timer Unit
The following table shows the related flags of the Timer Unit in alphabetic order.
Flags TAutoRestart TimerValue TimerReloadValue TPreScaler TRunning TStartNow TStartTxBegin TStartTxEnd TStopNow TStopRxBegin TStopRxEnd
Register TimerClock TimerValue TimerReload TimerClock SecondaryStatus Control TimerControl TimerControl Control TimerControl TimerControl
Address 0x2A, bit 5 0x0C, bits 7-0 0x2C, bits 7-0 0x2A, bits 4-0 0x05, bit 7 0x09, bit 1 0x2B, bit 0 0x2B, bit 1 0x09, bit 2 0x2B, bit 2 0x2B, bit 3
Table 9-1 Registers associated with the Timer Unit
78
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
10
POWER REDUCTION MODES
10.1 Hard Power Down A Hard Power Down is enabled with HIGH on pin RSTPD. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pads and defined internally (except pin RSTPD itself). The output pins are frozen at a certain value. This is shown in the following table:
SYMBOL OSCIN IRQ RFU SIGOUT TX1 TX2 NWR NRD NCS D0 to D7 ALE A0 A1 A2 AUX RX VMID RSTPD OSCOUT PIN 1 2 3 4 5 7 9 10 11 13 to 20 21 22 23 24 27 29 30 31 32 TYPE I O I O O O I I I I/O I I/O I I O I A I O DESCRIPTION Not separated from input, pulled to AVSS High impedance Separated from Input LOW HIGH LOW Separated from Input Separated from Input Separated from Input Separated from Input Separated from Input Separated from Input Separated from Input Separated from Input High impedance Not changed Pulled to AVDD Not changed HIGH
Table 10-1: Signal on Pins during Hard Power Down
10.2 Soft Power Down This mode is immediately entered by setting bit PowerDown in the Control-Register. All internal current sinks are switched off (including the oscillator buffer). Different from the Hard Power Down Mode, the digital input buffers are not separated from the input pads but keep their functionality. The digital output pins do not change their state. After resetting bit PowerDown in the Control-Register it needs 512 clocks until the Soft Power Down mode is left. This is indicated by the PowerDown bit itself. Resetting it does not immediately clear it, but it is cleared automatically by the SL RC400 when the Soft Power Down Mode is left. Note: If the internal oscillator is used, you have to take into account that it is supplied by AVDD and it will take a certain time tosc until the oscillator is stable.
79
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
10.3 Stand By Mode This mode is immediately entered by setting bit StandBy in the Control-Register. All internal current sinks are switched off (including the internal digital clock buffer but except the oscillator buffer). Different from the Hard Power Down Mode, the digital input buffers are not separated from the input pads but keep their functionality. The digital output pins do not change their state. Different from the Soft Power Down Mode, the oscillator does not need time to wake up. After resetting bit StandBy in the Control-Register it needs 4 clocks on pin OSCIN until the Stand By Mode is left. This is indicated by the StandBy bit itself. Resetting it does not immediately clear it, but it is cleared automatically by the SL RC400 when the Stand By Mode is left.
10.4 Receiver Power Down It is power saving to switch off the receiver circuit when it is not needed and switched it on again right before data is to be received from the label. This is done automatically by setting bit RxAutoPD to 1. If it is set to 0 the receiver is continuously switched on.
80
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
11
START UP PHASE
The phases executed during the start up are shown in the following figure:
Start Up Phase tPD tReset tInit
States
Hard Power Down Phase
Reset Phase
Initialising Phase
Ready
Figure 11-1: Start Up Procedure
11.1 Hard Power Down Phase The Hard Power Down Phase is active during the following cases: * * * Power On Reset caused by power up at pin DVDD (active while DVDD is below the digital reset threshold) Power On Reset caused by power up at pin AVDD (active while AVDD is below the analog reset threshold) A HIGH level on pin RSTPD (active while pin RSTPD is HIGH)
11.2 Reset Phase The Reset Phase follows the Hard Power Down Phase automatically. It takes 512 clocks. During the Reset Phase, some of the register bits are preset by hardware. The respective reset values are given in the description of each register (see 5.2.). Note: If the internal oscillator is used, you have to take into account that it is supplied by AVDD and that it will take a certain time tosc until the oscillator is stable. 11.3 Initialising Phase The Initialising Phase follows the Reset Phase automatically. It takes 128 clocks. During the Initialising Phase the content of the EPROM blocks 1 and 2 is copied into the registers 10hex to 2Fhex (see 6.3.). Note: At production test, the SL RC400 is initialised with default configuration values. This reduces the -Processors effort for configuring the device to a minimum.
81
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
11.4 Initialising the Parallel Interface-Type For the different connections for the different -Processor interface types (see 4.3), a certain initialising sequence shall be applied to enable a proper -Processor interface type detection and to synchronise the -Processor's and the SL RC400's Start Up. During the whole Start Up Phase, the Command value reads as 3Fhex . At the end of the Initialising Phase the SL RC400 enters the Idle Command automatically. Consequently the Command value changes to 00hex . To ensure proper detection of the -Processor interface, the following sequence shall be executed: * * * Read from the Command-Register until the six bit register value for Command is 00hex . The internal initialisation phase is now completed and the SL RC400 is ready to be controlled. Write the value 80hex to the Page-Register to initialise the -Processor interface. Read the Command-Register. If its value is 00hex the -Processor interface initialisation was successful.
After interface initialisation, the linear addressing mode can be activated by writing 0x00 to the page register(s).
82
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
12
OSCILLATOR CIRCUITRY
SL RC400
OSCOUT OSCIN
13.56 MHz 15 pF 15 pF
Figure 12-1: Quartz Connection
The clock applied to the SL RC400 acts as time basis for the coder and decoder of the synchronous system. Therefore stability of clock the frequency is an important factor for proper performance. To obtain highest performance, clock jitter has to be as small as possible. This is best achieved by using the internal oscillator buffer with the recommended circuitry. If an external clock source is used, the clock signal has to be applied to pin OSCIN. In this case special care for clock duty cycle and clock jitter is needed and the clock quality has to be verified. It needs to be in accordance with the specifications in chapter 19.5.3. Remark: It is recommend not to use an external clock source.
83
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
13
TRANSMITTER PINS TX1 AND TX2
The signal delivered on TX1 and TX2 is the 13.56 MHz carrier frequency modulated by an envelope signal. It can be used to drive an antenna directly, using a few passive components for matching and filtering (see chapter 17). For that, the output circuitry is designed with an very low impedance source resistance. The signal of TX1 and TX2 can be controlled via the TxControl Register.
13.1 Configuration of TX1 and TX2 The configuration possibilities of TX1 are described in the table below:
Register Configuration in TxControl TX1RFEn 0 1 1 X 0 1 LOW (GND) 13.56 MHz carrier frequenzy modulated 13.56 MHz carrier frequenzy Envelope Signal on TX1
Table 13-1: Configurations of Pin TX1
The configuration possibilities of TX2 are described in the table below:
Register Configuration in TxControl TX2RFEn 0 TX2CW X InvTX2 X 0 0 1 1 1 0 1 1 X X Envelope X 0 1 0 Signal on TX2 LOW (GND) 13.56 MHz carrier frequenzy modulated 13.56 MHz carrier frequenzy 13.56 MHz carrier frequenzy modulated, 180 phase shift relative to TX1 13.56 MHz carrier frequenzy, 180 phase shift relative to TX1 13.56 MHz carrier frequenzy 13.56 MHz carrier frequenzy, 180 phase shift relative to TX1
Table 13-2: Configurations of Pin TX2
13.2 Operating Distance versus Power Consumption The user has the possibility to find a trade-off between maximum achievable operating distance and power consumption by using different antenna matching circuits as described in 17.3.1 and/or by varying the supply voltage at the antenna driver supply pin TVDD.
84
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
13.2.1 ANTENNA DRIVER OUTPUT SOURCE RESISTANCE The output source conductance of TX1 and TX2 for driving a HIGH level may be adjusted via the value GsCfgCW in the CwConductance Register in the range from about 1 up to 100 Ohm. The values given are relative to the reference resistance Rs rel, that is measured during production test and stored in the SL RC400 EPROM. It can be obtained from the Product Information Field (see chapter 6.2). The electrical specification can be found in chapter 19.4.3.
13.2.1.1 Source Resistance Table
GsConfCW 0 16 32 48 1 17 2 3 33 18 4 5 19 6 7 49 34 20 8 9 21 10 11 35 22 12 13 23 14 50 36 15 EXPGsConfCW 0 1 2 3 0 1 0 0 2 1 0 0 1 0 0 3 2 1 0 0 1 0 0 2 1 0 0 1 0 3 2 0 MANT GsConfCW 0 0 0 0 1 1 2 3 1 2 4 5 3 6 7 1 2 4 8 9 5 A B 3 6 C D 7 E 2 4 F Rs rel 8 8 8 8 1,0000 0,5217 0,5000 0,3333 0,2703 0,2609 0,2500 0,2000 0,1739 0,1667 0,1429 0,1402 0,1351 0,1304 0,1250 0,1111 0,1043 0,1000 0,0909 0,0901 0,0870 0,0833 0,0769 0,0745 0,0714 0,0701 0,0676 0,0667 GsConfCW 24 25 37 26 27 51 38 28 29 39 30 52 31 40 41 53 42 43 54 44 45 55 46 47 56 57 58 59 60 61 62 63 EXPGsConfCW 1 1 2 1 1 3 2 1 1 2 1 3 1 2 2 3 2 2 3 2 2 3 2 2 3 3 3 3 3 3 3 3 MANT GsConfCW 8 9 5 A B 3 6 C D 7 E 4 F 8 9 5 A B 6 C D 7 E F 8 9 A B C D E F Rs rel 0,0652 0,0580 0,0541 0,0522 0,0474 0,0467 0,0450 0,0435 0,0401 0,0386 0,0373 0,0350 0,0348 0,0338 0,0300 0,0280 0,0270 0,0246 0,0234 0,0225 0,0208 0,0200 0,0193 0,0180 0,0175 0,0156 0,0140 0,0127 0,0117 0,0108 0,0100 0,0093
Table 13-3: Source Resistance of n-Channel Driver Transistor of TX1 and TX2 vs. GsConfCW
85
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
13.2.1.2 Formula for the Source Resistance The relative resistance Rs rel is about
Rs rel =
1 MANTGsConfCW ( 77 ) 40
EXP GsConfCW
13.2.1.3 Calculating the Effective Source Resistance
13.2.1.3.1 Wiring Resistance
Wiring and bonding adds a constant offset to the driver resistance, that is relevant if TX1 and TX2 are switched to low impedance.
Rs wire,TX 1 500 m
13.2.1.3.2 Effective Resistance
The source resistances of the driver transistors found in the Product Information Field (see 6.2) are measured at production test with GsModCW set to 01hex . To get the driver resistance for a specific value set in GsModCW the following formula may be used:
Rs x = (Rs ref , max, n - Rs wire,TX 1 ) Rs rel + Rs wire,TX 1 .
86
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
13.3 Changing the Modulation Index The following table shows the modulation index, if a 50 ohm antenna is used and GsCfgCW is set to 0x3F. To change the modulation index the GsCfgMod register has to be changed similar as the GsCfgCW register.
GsCfgMod rel. resistance Mod. index GsCfgMod rel. resistance Mod. index
Rrel(during modulation) Rant=50 0x00 0x10 0x20 0x30 0x01 0x11 0x02 0x03 0x21 0x12 0x04 0x05 0x13 0x06 0x07 0x31 0x22 0x14 0x08 0x09 0x15 0x0A 0x0B 0x23 0x16 0x0C 0x0D 0x17 0x0E 0x32 0x24 0x0F Infite Infite Infite Infite 1,000 0,522 0,500 0,333 0,270 0,261 0,250 0,200 0,174 0,167 0,143 0,140 0,135 0,130 0,125 0,111 0,104 0,100 0,091 0,090 0,087 0,083 0,077 0,075 0,071 0,070 0,068 0,067 43,45% 28,44% 27,57% 20,08% 16,83% 16,33% 15,73% 12,88% 11,32% 10,88% 9,38% 9,21% 8,89% 8,59% 8,23% 7,32% 6,86% 6,57% 5,95% 5,89% 5,68% 5,43% 4,98% 4,81% 4,59% 4,50% 4,32% 4,26% 0x18 0x19 0x25 0x1A 0x1B 0x33 0x26 0x1C 0x1D 0x27 0x1E 0x34 0x1F 0x28 0x29 0x35 0x2A 0x2B 0x36 0x2C 0x2D 0x37 0x2E 0x2F 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F
Rrel(during modulation) Rant=50 0,065 0,058 0,054 0,052 0,047 0,047 0,045 0,043 0,040 0,039 0,037 0,035 0,035 0,034 0,030 0,028 0,027 0,025 0,023 0,023 0,021 0,020 0,019 0,018 0,018 0,016 0,014 0,013 0,012 0,011 0,010 0,009 4,15% 3,63% 3,35% 3,22% 2,87% 2,82% 2,69% 2,58% 2,33% 2,22% 2,12% 1,95% 1,93% 1,86% 1,58% 1,43% 1,35% 1,17% 1,08% 1,01% 0,88% 0,82% 0,77% 0,67% 0,63% 0,48% 0,36% 0,26% 0,18% 0,11% 0,05% 0,00%
Note: If the output source conductance (GsCfgCW) has been changed GsCfgMod must also be changed to get the same modulation index.
87
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
13.4 Pulse Width The envelope carries the information of the data signal, that shall be transmitted to the label. This is done by coding the data signal according to the 1 out of 256, RZ or 1 out of 4 code. Furthermore, each pause of the coded signal again is coded as a pulse of certain length. The width of this pulse can be adjusted by means of the ModWidth Register. The pulse length is calculated by
TPulse = 2
where fc = 13.56MHz.
ModWidth + 1 fC
88
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
14
RECEIVER CIRCUITRY
14.1 General The SL RC400 employs an integrated quadrature-demodulation circuit which extracts the sub-carrier signal from the 13.56 MHz ASK-modulated signal applied to pin RX. The quadrature-demodulator uses two different clocks, Q- and I-clock, with a phase shift of 90 between them. Both resulting subcarrier signals are amplified, filtered and forwarded to the correlation circuitry. The correlation results are evaluated, digitised and passed to the digital circuitry. For all processing units various adjustments can be made to obtain optimum performance.
14.2 Block Diagram Figure 14-1 shows the block diagram of the receiver circuitry. The receiving process includes several steps. First the quadrature demodulation of the carrier signal of 13.56 MHz is done. To achieve an optimum in performance an automatic clock Q calibration is recommended (see 14.3.1). The demodulated signal is amplified by an adjustable amplifier. A correlation circuit calculates the degree of similarity between the expected and the received signal. The bit phase register allows to align the position of the correlation intervals with the bit grid of the received signal. In the evaluation and digitizer circuitry the valid bits are detected and the digital results are send to the FIFO register. Several tuning steps in this circuit are possible.
ClockQDelay[4:0]
ClockQCalib
ClockQ180 Gain[1:0]
BitPhase[7:0]
CollLevel[3:0] MinLevel[3:0]
RcvClkSelI
RxWait[7:0]
I to Q Conversion
clock I-clock Q-clock s_valid RX
13.56 MHz Demodulator
Correlation Circuitry
Evaluation and Digitizer Circuitry
s_data s_coll s_clock
VRxFollQ VRxFollI
VRxAmpQ VRxAmpI
VCorrNI VCorrDI
VCorrNQ VEvalR VEvalL
VCorrDQ
to TestAna OutSel
Figure 14-1: Block Diagram of Receiver Circuitry
The user may observe the signal on its way through the receiver as shown in the block diagram above. One signal at a time may be routed to pin AUX using the TestAnaSelect-Register as described in 18.3.
89
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
14.3 Putting the Receiver into Operation In general, the default settings programmed into the Start Up Initialisation File are suitable to use the SL RC400 for data communication with I*CODE labels. However, in some environments specific user settings may achieve better performance.
14.3.1 AUTOMATIC CLOCK-Q CALIBRATION The quadrature demodulation concept of the receiver generates a phase signal I-clock and a 90 shifted quadrature signal Q-clock. To achieve an optimum demodulator performance, the Q- and the I-clock have to have a difference in phase of 90. After the reset phase of the SL RC400, a calibration procedure is done automatically. It is possible to have an automatic calibration done at the ending of each Transceive command. To do so, the ClkQCalib bit has to be configured to a value of 0. Configuring this bit to a constant value of 1 disables all automatic calibrations except the one after the reset sequence. It is also possible to initiate one automatic calibration by software. This is done with a 0 to 1 transition of bit ClkQCalib. The details:
calibration impulse from reset sequence calibration impulse from ending of TRANSEIVE command
a rising edge initiates a clock Q calibration
the ClkQCalib bit
Note: The duration of the automatic clock Q calibration is at most 65 oscillator periods which is approx. 4,8s. The value of ClkQDelay is proportional to the phase shift between the Q- and the I-clock. The status flag ClkQ180Deg shows, that the phase shift between the Q- and the I-clock is greater than 180. Notes: * * * The startup configuration file enables an automatically Q-clock calibration after the reset. While ClkQCalib is 1, no automatic calibration is done. Therefore leaving this bit 1 can be used to permanently disable the automatic calibration. It is possible to write data to ClkQDelay via the -Processor. The aim could be a disabling of the automatic calibration and to pre-set the delay by software. But notice, that configuring the delay value by software requires that bit ClkQCalib has already been set to 1 before and that a time interval of at least 4.8s has elapsed since then. Each delay value must be written with the ClkQCalib bit set to 1. If ClkQCalib is 0 the configured delay value will be overwritten by the next interval automatic calibration.
90
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
14.3.2 AMPLIFIER The demodulated signal has to be amplified with the variable amplifier to achieve the best performance. The gain of the amplifiers can be adjusted by means of the register bits Gain[1:0]. The following gain factors are selectable:
Register Setting 0 1 2 3 Gain Factor (Simulation Results) 22 35 82 130 Gain Factor [dB] (Simulation Results) 26.9 30.9 38.3 42.2
Table 14-1: Gain Factors for the Internal Amplifier
91
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
14.3.3 CORRELATION CIRCUITRY The correlation circuitry calculates the degree of matching between the received and an expected signal. The output is a measure for the amplitude of the expected signal in the received signal. This is done for both, the Q- and the I-channel. The correlator delivers two outputs for each of the two input channels, resulting in four output signals in total. For optimum performance, the correlation circuitry needs the phase information for the signal coming from the label. This information has to be defined by the -Processor by means of the register BitPhase[7:0]. This value defines the phase relation between the transmitter and receiver clock in multiples of tBitPhase = 1/13.56 MHz.
14.3.4 EVALUATION AND DIGITIZER CIRCUITRY For each bit-half of the Manchester coded signal the correlation results are evaluated. The evaluation and digitizer circuit decides from the signal strengths of both bit-halves, whether the current bit is valid, and, if it is valid, the value of the bit itself or whether the current bit-interval contains a collision. To do this in an optimum way, the user may select the following levels: * * MinLevel: Defines the minimum signal strength of the stronger bit-half's signal for being considered valid. CollLevel: Defines the minimum signal strength that has to be exceeded by the weaker half-bit of the Manchester-coded signal to generate a bit-collision. If the signal's strength is below this value, a 1 and 0 can be determined unequivocally. CollLevel defines the minimum signal strength relative to the amplitude of the stronger half-bit.
After transmission of data, the label is not allowed to send its response before a certain time period, called frame guard time in the standard ISO 15693 (similar to I*CODE1). The length of this time period after transmission shall be set in the RxWait-Register. The RxWait-Register defines when the receiver is switched on after data transmission to the label in multiples of one bit-duration. If register bit RcvClkSelI is set to 1, the I-clock is used to clock the correlator and evaluation circuits. If set to 0, the Q-clock is used. Note: It is recommended to use the Q-clock.
92
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
15
SERIAL SIGNAL SWITCH
15.1 General Two main blocks are implemented in the SL RC400. A digital circuitry, comprising state machines, coder and decoder logic and so on and an analog circuitry with the modulator and antenna drivers, receiver and amplification circuitry. The interface between these two blocks can be configured in the way, that the interfacing signals may be routed to the pin SIGOUT.
15.2 Block Diagram Figure 15-1 describes the serial signal switches. Three different switches are implemented in the serial signal switch in order to use the SL RC400 in different configurations. The serial signal switch may also be used during the design In phase or for test purposes to check the transmitted and received data. Chapter 18.2, describes analog test signals as well as measurements at the serial signal switch.
0
0 1 2 3 2 Modulator Source Tx1
Serial Data Out
1 out of 256 or RZ or 1 out of 4
1 Envelope RFU
Modulator
Driver
Tx2
(Part of) Serial Data Processing
(Part of) Analog Circuitry
0
0 Manchester Out Manchester with Subcarrier
Serial Data In
Manchester Decoder
1 Internal 2 RFU 3 RFU Transmitt NRZ 2 Envelope Decoder Source 0 1
Subcarrier Demodulator
Carrier Demodulator
Rx
Manchester
RFU 6
0
1
2
3
4
5
7
RFU
0
1
Serial Signal Switch
SIGOut
SignalTo SigOut
Figure 15-1: Serial Signal Switch
The following chapters describe the relevant registers used to configure and control the serial signal switch.
93
SigOut Select Digital Test Signal
3
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
15.3 Registers Relevant for the Serial Signal Switch The flags DecoderSource define the input signal for the internal Manchester decoder in the following way:
DecoderSource 0 1 2 3 Constant 0 Output of the analog part. This is the default configuration. RFU RFU Input Signal for Decoder
Table 15-1: Values for DecoderSource
ModulatorSource defines the signal that modulates the transmitted 13.56 MHz carrier frequenzy. The modulated signal drives the pins TX1 and TX2.
ModulatorSource 0 1 2 3 Input Signal for Modulator Constant 0 (carrier frequency off at pin TX1 and TX2). Constant 1 (continuous carrier frequency delivered at pin TX1 and TX2). Modulation signal (envelope) from the internal coder. This is the default configuration. RFU
Table 15-2: Values for ModulatorSource
SIGOUTSelect defines the input signal for the internal Manchester decoder in the following way:
SIGOUTSelect 0 1 2 3 4 5 6 7 Constant 0 Constant 1 Modulation signal (envelope) from the internal coder. Serial data stream that is to be transmitted (same as for SIGOUTSelect = 2, but not coded by the "selected" pulse coder yet). Output signal of the receiver circuit (label modulation signal regenerated and delayed) Output signal of the sub-carrier demodulator (Manchester-coded label signal) RFU RFU Signal Routed to Pin SIGOUT
Table 15-3: Values for SIGOUTselect
Note: To use SIGOUTSelect, the value of test signal control bit SignalToSIGOUT has to be 0.
94
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
16
SL RC400 COMMAND SET
16.1 General Description The SL RC400 behaviour is determined by an internal state machine that is capable to perform a certain set of commands. These commands are started by writing the according command-code to the CommandRegister. Arguments and/or data necessary to process a command are exchanged via the FIFO buffer.
16.2 General Behaviour * * * * Each command, that needs a data stream (or data byte stream) as input will immediately process the data it finds in the FIFO buffer. Each command, that needs a certain number of arguments will start processing only when it has received the correct number of arguments via the FIFO buffer. The FIFO buffer is not cleared automatically at command start. Therefore, it is also possible to write the command arguments and/or the data bytes into the FIFO buffer and start the command afterwards. Each command (except the StartUp-Command) may be interrupted by the -Processor by writing a new command code into the Command-Register e.g.: the Idle-Command.
95
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
16.3 SL RC400 Commands Overview
Command Code Action Runs the Reset- and Initialisation Phase. StartUp 3Fhex Note: This command can not be activated by software, but only by a Power-On or Hard Reset No action: cancels current command execution. Transmits data from the FIFO buffer to the label. Activates Receiver Circuitry. Note: Before the receiver actually starts, the state machine waits until the time configured in the register RcvWait has passed. Note: This command may be used for test purposes only, since there is no timing relation to the TransmitCommand. Transmits data from FIFO buffer to the label and activates automatically the receiver after transmission. Transceive 1Ehex Note: Before the receiver actually Data Stream starts, the SL RC400 waits until the time configured in the register RcvWait has passed. Note: This command is the combination of Transmit and Receive WriteE2 01hex Gets data from FIFO buffer and writes it to the internal EPROM. Reads data from the internal EPROM and puts it into the FIFO buffer. Reads data from EPROM and initialises the SL RC400 registers. Activates the CRC-Coprocessor. CalcCRC 12hex Note: The result of the CRC calculation can be read from the registers CRCResultLSB and CRCResultMSB Data Byte-Stream 16.5 Start Address LSB Start Address MSB Data Byte Stream Start Address LSB Start Address MSB Number of Data Bytes Start Address LSB Start Address MSB 16.5 Data Stream 16.4.3 Data Stream 16.3.2 Arguments and Data passed via FIFO Returned Data via FIFO see Chapter
Idle Transmit
00hex 1Ahex
-
-
16.3.3 16.4.1
Receive
16hex
-
Data Stream
16.4.2
ReadE2
03hex
Data Bytes
16.5.2
LoadConfig
07hex
-
16.6.1
Table 16-1: SL RC400 Command Overview
96
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
16.3.1 BASIC STATES 16.3.2 STARTUP COMMAND 3FHEX
Command Code hex Action Runs the Reset- and Initialisation Phase StartUp 3F Note: This command can not be activated by software, but only by a Power-On or Hard Reset Arguments and Data Returned Data
The StartUp-Command runs the Reset- and Initialisation Phase. It does not need or return any data. It can not be activated by the -Processor but is started automatically after one of the following events: * Power On Reset caused by power up at Pin DVDD * Power On Reset caused by power up at Pin AVDD * Negative Edge at Pin RSTPD
The Reset-Phase defines certain register bits by an asynchronous reset. The Initialisation-Phase defines certain registers with values taken from the EPROM. When the StartUp-Command has finished, the Idle-Command is entered automatically. Notes: * The -Processor must not write to the SL RC400 as long as the SL RC400 is busy executing the StartUp-Command. To ensure this, the -Processor shall poll for the Idle-Command to determine the end of the Initialisation Phase (see also chapter 11.4). As long as the StartUp-Command is active, only reading from page 0 of the SL RC400 is possible. The StartUp-Command can not be interrupted by the -Processor.
* *
16.3.3 IDLE COMMAND 00HEX
Command Idle Code hex 00 Action No action: cancels current command execution Arguments and Data Returned Data -
The Idle-Command switches the SL RC400 to its inactive state. In this Idle-state it waits for the next command. It does not need or return any data. The device automatically enters the Idle-state when a command finishes. In this case the SL RC400 simultaneously initiates an interrupt request by setting bit IdleIRq. Triggered by the -Processor, the Idle-Command may be used to stop execution of all other commands (except the StartUp Command). In that case no IdleIRq is generated. Remark: Stopping a command with the Idle Command does not clear the FIFO buffer content.
97
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
16.4 Commands for Label Communication The SL RC400 is a fully ISO 15693 and I*CODE1 compliant reader IC. The following chapter describe the command set for label communication in general. 16.4.1 TRANSMIT COMMAND 1A HEX
Command Transmit Code hex 1A Action Transmits data from FIFO buffer to the label Arguments and Data Data Stream Returned Data -
The Transmit-Command takes data from the FIFO buffer and forwards it to the transmitter. It does not return any data. The Transmit-Command can only be started by the -Processor.
16.4.1.1 Working with the Transmit Command To transmit data one of the following sequences may be used: 1. All data, that shall be transmitted to the label is written to the FIFO while the Idle-Command is active. After that, the command code for the Transmit-Command is written to the Command-Register. Note: This is possible for transmission of data with a length of up to 64 bytes. The command code for the Transmit-Command is written to Command-Register first. Since no data is available in the FIFO, the command is only enabled but transmission is not triggered yet. Data transmission really starts with the first data byte written to the FIFO. To generate a continuous data stream on the RF-interface, the -Processor has to put the next data bytes to the FIFO in time. Note: This allows transmission of data of any length but requires that data is available in the FIFO in time. A part of the data, that shall be transmit to the label is written to the FIFO while the Idle-Command is active. After that, the command code for the Transmit-Command is written to the Command-Register. While the Transmit-Command is active, the -Processor may feed further data to the FIFO, causing the transmitter to append it to the transmitted data stream. Note: This enables transmission of data of any length but requires that data is available in the FIFO in time.
2.
3.
When the transmitter requests the next data byte to keep the data stream on the RF-interface continuous but the FIFO buffer is empty, the Transmit-Command automatically terminates. This causes the internal state machine to change its state from Transmit to Idle. If data transmission to the label is finished, the SL RC400 sets the flag TxIRq to signal it to the -Processor. Remark: If the -Processor overwrites the transmit code in the Command-Register with the Idle-Command or any other command, transmission stops immediately with the next clock cycle. This may produce output signals that are not according to the standard ISO 15693 or the I*CODE1 protocol.
98
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
16.4.1.2 RF-Channel Redundancy and Framing Each transmitted ISO 15693 frame consists of a SOF (start of frame) pattern, followed by the data stream and is closed by an EOF (end of frame) pattern. All I*CODE1 command frames consists of a START PULSE followed by the data stream. The I*CODE1 commands have a fix length and no EOF is needed. These different phases of the transmit sequence may be monitored by watching ModemState of PrimaryStatusRegister (see 16.4.4). Depending on the setting of bit TxCRCEn in the ChannelRedundancy-Register a CRC is calculated and appended to the data stream. The CRC is calculated according the settings in the ChannelRedundancy Register. 16.4.1.3 Transmission of Frames with more than 64 Bytes To generate frames with more than 64 bytes, the -Processor has to write data into the FIFO buffer while the Transmit Command is active. The state machine checks the FIFO status when it starts transmitting the last bit of the actual data stream (the check time is marked below with arrows).
TxLastBits
TxLastBits = 0
FIFO Length
0x01
0x00
FIFO empty
TxData
Bit7 Bit0
Bit7 Bit0
Bit7
Check FIFO empty
Accept Further Data
Figure 16-1: Timing for Transmitting Byte Oriented Frames
As long as the internal signal `Accept Further Data' is 1 further data may be loaded into the FIFO. The SL RC400 appends this data to the data stream transmitted via the RF-interface. If the internal signal `Accept Further Data' is 0 the transmission will terminate. All data written into the FIFO buffer after `Accept Further Data' went 0 will not be transmitted anymore, but remain in the FIFO buffer.
99
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
16.4.2 RECEIVE COMMAND 16HEX
Command Receive Code hex 16 Action Activates Receiver Circuitry Arguments and Data Returned Data Data Stream
The Receive-Command activates the receiver circuitry. All data received from the RF interface is returned via the FIFO buffer. The Receive-Command can be started either by the -Processor or automatically during execution of the Transceive-Command. Note: This command may be used for test purposes only, since there is no timing relation to the TransmitCommand. 16.4.2.1 Working with the Receive Command After starting the Receive Command the internal state machine decrements the value set in the RxWaitRegister with every bit-clock. From 3 down to 1 the analog receiver circuitry is prepared and activated. When the counter reaches 0, the receiver starts monitoring the incoming signal at the RF-interface. If the signal strength reaches a level higher than the value set in the MinLevel-Register it finally starts decoding. The decoder stops, if no more signal can be detected on the receiver input pin Rx. The decoder indicates termination of operation by setting bit RxIRq. The different phases of the receive sequence may be monitored by watching ModemState of the PrimaryStatus-Register (see 16.4.4). Note: Since the counter values from 3 to 0 are necessary to initialise the analog receiver circuitry the minimum value for RxWait is 3.
16.4.2.2 RF-Channel Redundancy and Framing For ISO 15693 the decoder expects a SOF pattern at the beginning of each data stream. If a SOF is detected, it activates the serial to parallel converter and gathers the incoming data bits. For I*CODE1 the decoder do not expects a SOF pattern at the beginning of each data stream. It activates the serial to parallel converter with the first received bit of the data. Every completed byte is forwarded to the FIFO. If an EOF pattern (ISO15693) is detected or the signal strength falls below MinLevel set in the RxThreshold Register, the receiver and the decoder stop, the Idle-Command is entered and an appropriate response for the Processor is generated (interrupt request activated, status flags set). If bit RxCRCEn in the ChannelRedundancy Register is set a CRC block is expected. The CRC block may be one byte or two bytes according to bit CRC8 in the ChannelRedundancy Register. Remark: The received CRC block is not forwarded to the FIFO buffer if it is correct. This is realised by shifting the incoming data bytes through an internal buffer of either one or two bytes (depending on the defined CRC). The CRC block remains in this internal buffer. As a consequence all data bytes are available in the FIFO buffer one or two bytes delayed. If the CRC fails all received bytes are forwarded to the FIFO buffer (including the faulty CRC itself).
100
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
16.4.2.3 Collision Detection If more than one label is within the RF-field during the label selection phase, they will respond simultaneously. The SL RC400 supports the algorithm defined in ISO 15693 as well as the I*CODE1 anticollision algorithm to resolve data-collisions of label serial numbers by doing the so-called anti-collision procedure. The basis for this is the ability to detect bit-collisions. Bit-collision detection is supported by the used bit-coding scheme, namely the Manchester-coding. If in the first and second half-bit of a bit a sub-carrier modulation is detected, instead of forwarding a 1 or a 0 a bit collision will be signalled. To distinguish a 1 or 0-bit from a bit-collision, the SL RC400 uses the setting of CollLevel. If the amplitude of the half-bit with smaller amplitude is larger than defined by CollLevel, the SL RC400 indicates a bit-collision. If a bit-collision is detected, the error flag CollErr is set. Independent from the detected collision the receiver continues receiving the incoming data stream. In case of a bit-collision, the decoder forwards 1 at the collision position. Note: As an exception, if bit ZeroAfterColl is set, all bits received after the first bit-collision are forced to zero, regardless whether a bit-collision or an unequivocal state has been detected. This feature eases for the software to carry out the anti-collision procedure defined in ISO 15693. When the first bit collision in a frame is detected, the bit position of this collision is stored in the CollPos Register.
The collision position follows the table below:
Collision in Bit SOF LSBit of LSByte ... MSBit of LSByte LSBit of second Byte ... MSBit of second Byte LSBit of third Byte ... Value of CollPos 0 1 ... 8 9 ... 16 17 ...
Table 16-2: Returned Values for Bit Collision Positions
If a collision is detected in the SOF a frame error is reported and no data is forwarded to the FIFO buffer. In this case the receiver continues to monitor the incoming signal and generates the correct notifications to the -Processor when the ending of the faulty input stream is detected. This helps the -Processor to determine the time when it is allowed next to send anything to the label.
101
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
16.4.2.4 Communication Errors The following table shows which event causes the setting of error flags:
Cause Received data did not start with a SOF pattern. The CRC block is not equal the expected value. The received data is shorter than the CRC block. A collision is detected. Bit, that is set FramingErr CRCErr CRCErr CollErr
Table 16-3: Communication Error Table
16.4.3 TRANSCEIVE COMMAND 1E HEX
Command Transceive Code hex 1E Action Transmits data from FIFO buffer to the label and then activates automatically the receiver Arguments and Data Data Stream Returned Data Data Stream
The Transceive-Command first executes the Transmit-Command (see 16.4.1) and then automatically starts the Receive-Command (see 16.4.2). All data that shall be transmitted is forwarded via the FIFO buffer and all data received is returned via the FIFO buffer. The Transceive-Command can be started only by the -Processor. Note: To adjust the timing relation between transmitting and receiving, the RxWait Register is used to define the time delay from the last bit transmitted until the receiver is activated. Furthermore, the BitPhase Register determines the phase-shift between the transmitter and the receiver clock. 16.4.4 STATES OF THE LABEL COMMUNICATION The actual state of the transmitter and receiver state machine can be fetched from ModemState in the PrimaryStatus Register. The assignment of ModemState to the internal action is shown in the following table:
ModemState 000 001 010 011 100 101 110 111 Name of State Idle TxSOF TxData TxEOF GoToRx1 GoToRx2 PrepareRx AwaitingRx Receiving Description Neither the transmitter nor the receiver is in operation, since none of them is started or the transmitter has not got input data Transmitting the `Start Of Frame' Pattern Transmitting data from the FIFO buffer (or redundancy check bits) Transmitting the `End Of Frame' Pattern Intermediate state passed, when receiver starts Intermediate state passed, when receiver finishes Waiting until the time period selected in the RxWait Register has expired Receiver activated; Awaiting an input signal at pin Rx Receiving data
Table 16-4: Meaning of ModemState 102 Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
16.4.5 STATE DIAGRAM FOR THE LABEL COMMUNICATION
Command = (Transmit OR Receive OR Transceive)
Idle (000)
F Co IFO (Tr mm not e an an m sm d = pty it O AN R D Tra ns ce ive )
Co m Re man ce d = ive
TxSOF (001)
GoToRx1 (100)
next bit clock SOF transmitted
TxData (010)
PrepareRx (101)
Data transmitted
RxWaitCounter =0
RxMultiple = 1 && TimeSlotPeriod > 0 && TimeSlot Trigger && Data in FIFO
TxEOF (011)
AwaitingRx (110)
Signal Strength > MinLevel EOF transmitted AND Command = Transceive
Receiving (111)
EOF transmitted AND Command = Transmit Frame Received
End of Receive frame && RxMultiple = 0 && TimeSlotPeriod = 0
GoToRx2 (100)
Set CommandRegister = Idle (000)
RxMultiple = 0 && TimeSlotPeriod > 0 && TimeSlot Trigger && Data in FIFO
Idle (000)
Preparing to send the Quit value
Remark: I*CODE1 do not have a SOF and a EOF 103 Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
16.5 Commands to Access the EPROM 16.5.1 WRITEE2 COMMAND 01HEX 16.5.1.1 Overview
Arguments and Data passed via FIFO Start Address LSB Start Address MSB Data Byte Stream Returned Data via FIFO -
Command
Code hex
Action
WriteE2
01
Get data from FIFO buffer and write it to the EPROM
The WriteE2-Command interprets the first two bytes in the FIFO buffer as EPROM starting byte-address. Any further bytes are interpreted as data bytes and are programmed into the EPROM, starting from the given EPROM starting byte-address. This command does not return any data. The WriteE2-Command can only be started by the -Processor. It will not stop automatically but has to be stopped explicitly by the -Processor by issuing the Idle-Command. 16.5.1.2 Programming Process One byte up to 16 byte can be programmed into the E PROM in one programming cycle. The time needed will be in any case about 5.8ms. The state machine copies all data bytes prepared in the FIFO buffer to the EPROM input buffer. The internal EPROM input buffer is 16 byte long which is equal the block size of the EPROM. A programming cycle is started either if the last position of the EPROM input buffer is written or if the last byte of the FIFO buffer has been fetched. As long as there are unprocessed bytes in the FIFO buffer or the EPROM programming cycle still is in progress, the flag E2Ready is 0. If all data from the FIFO buffer are programmed into the EPROM, the flag E2Ready is set to1. Together with the rising edge of E2Ready the interrupt request flag TxIRq indicates a 1. This may be used to generate an interrupt when programming of all data is finished. After the E2Ready bit is set to 1, the WriteE2-Command may be stopped by the -Processor by issuing the Idle-Command. Important: The WriteE2-Command must not be stopped by starting another command before the E2Ready flag is set to 1. Otherwise the content of the currently processed EPROM block will not be defined or in worst case the SL RC400 functionality is in-reversibly reduced.
2
104
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
16.5.1.3 Timing Diagram The following diagram shows programming of 5 bytes into the EPROM:
t prg,del
NWrite Data
WriteE2 command active
Write Adr E2 LSB Adr MSB Byte0 Byte1 Byte2 Byte3 Byte4 Idle Cmd
t prog
t prog
t prog
EPROM Programming E2Ready TxIRq
Programming Byte0
Programming Byte1, Byte2, and Byte3
Programming Byte4
Figure 16-3: Timing Diagram for EPROM programming
Explanation: It is assumed, that the SL RC400 finds and reads Byte 0 before the -Processor is able to write Byte 1 (t prog,del = 300 ns). This causes the SL RC400 to start the programming cycle, which needs about tprog = 2.9 ms. In the meantime the -Processor stores Byte 1 to Byte 4 to the FIFO buffer. Assuming, that the EPROM starting byte-address is e.g. 4Chex then Byte 0 is stored exactly there. The SL RC400 copies the following data bytes into the EPROM input buffer. Copying Byte 3, it detects, that this data byte has to be programmed at the EPROM byte-address 4Fhex . Since this is the end of the memory block, the SL RC400 automatically starts a programming cycle. In the next turn, Byte 4 will be programmed at the EPROM byteaddress 50hex . Since this is the last data byte, the flags (E2Ready and TxIRq) that indicate the end of the EPROM programming activity will be set. Although all data has been programmed into the E2PROM, the SL RC400 stays in the WriteE2-Command. Writing further data to the FIFO would lead to further EPROM programming, continuing at the EPROM byte-address 51hex . The command is stopped using the Idle-Command.
16.5.1.4 Error Flags for the WriteE2 Command Programming is inhibited for the EPROM blocks 0 (EPROM's byte-address 00hex to 0Fhex ). Programming to these addresses sets the flag AccessErr. No programming cycle is started (for the EPROM memory organisation refer to chapter 6.). It is strictly recommended to use only the described EPROM address area.
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
16.5.2 READE2 COMMAND 03HEX 16.5.2.1 Overview
Command ReadE2 Code hex 03 Action Reads data from EPROM and puts it to the FIFO buffer Arguments Start Address LSB Start Address MSB Number of Data Bytes Returned Data Data Bytes
The ReadE2-Command interprets the first two bytes found in the FIFO buffer as EPROM starting byte-address. The next byte specifies the number of data bytes that shall be returned. When all three argument-bytes are available in the FIFO buffer, the specified number of data bytes is copied from the EPROM into the FIFO buffer, starting from the given EPROM starting byte-address. The ReadE2-Command can be triggered only by the -Processor. It stops automatically when all data has been delivered. Note: It is strictly recommended to use only the described EPROM address area.
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
16.6 Diverse Commands 16.6.1 LOADCONFIG COMMAND 07HEX 16.6.1.1 Overview
Command LoadConfig Code hex 07 Action Reads data from EPROM and initialises the registers Arguments and Data Start Address LSB Start Address MSB Returned Data -
The LoadConfig-Command interprets the first two bytes found in the FIFO buffer as EPROM starting byte-address. When the two argument-bytes are available in the FIFO buffer, 32 bytes from the EPROM are copied into the SL RC400 control and configuration registers, starting at the given EPROM starting byte-address. The LoadConfig-Command can only be started by the -Processor. It stops automatically when all relevant registers have been copied. Note: It is strictly recommended to use only the described EPROM address area.
16.6.1.2 Register Assignment The 32 bytes of EPROM content, beginning with the EPROM starting byte-address, is written to the SL RC400 register 10hex up to register 2Fhex (for the EPROM memory organisation see 6). Note: The procedure for the register assignment is the same as it is for the Start Up Initialisation (see 11.3). The difference is, that the EPROM starting byte-address for the Start Up Initialisation is fixed to 10hex (Block 1, Byte 0). With the LoadConfig-Command it can be chosen.
16.6.1.3 Relevant Error Flags for the LoadConfig-Command Valid EPROM starting byte-addresses are in the range from 10hex up to 60hex .
16.6.2 CALCCRC COMMAND 12HEX 16.6.2.1 Overview
Command CalcCRC Code hex 12 Action Activates the CRC-Coprocessor Arguments and Data Data Byte-Stream Returned Data -
The CalcCRC-Command takes all data from the FIFO buffer as input bytes for the CRC-Coprocessor. All data stored in the FIFO buffer before the command is started will be processed. This command does not return any data via the FIFO buffer, but the content of the CRC-register can be read back via the CRCResultLSB-register and the CRCResultMSB-register. The CalcCRC-Command can only be started by the -Processor. It does not stop automatically but has to be stopped explicitly by the -Processor with the Idle-Command. If the FIFO buffer is empty, the CalcCRC-Command waits for further input from the FIFO buffer. Note: Do not use this command to calculate the Quit value for I?CODE1 tag's because this would terminate the Transceive command. 107 Preliminary
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
16.6.2.2 CRC-Coprocessor Settings For the CRC-Coprocessor the following parameters may be configured:
Parameter CRC Register Length CRC Algorithm Value 8 Bit or 16 Bit CRC 1 = Algorithm according ISO 15693 or according ISO/IEC3309 0 = algorithm according to I*CODE1 Bit-Processing Direction CRC Preset Value Shift the MSBit or LSBit first into the CRCregister Any CRCMSBFirst CRCPresetLSB, CRCPresetMSB ChannelRedundancy CRCPresetLSB, CRCPresetMSB Bit CRC8 CRC3309 Register ChannelRedundancy ChannelRedundancy
Table 16-5: CRC-Coprocessor Parameters
x8 + x4 + x3 + x2 + 1. 16 12 5 The CRC polynomial for the 16-bit CRC is fixed to x + x + x + 1 .
The CRC polynomial for the 8-bit CRC is fixed to 16.6.2.3 Status Flags of the CRC-Coprocessor The status flag CRCReady indicates, that the CRC-Coprocessor has finished processing of all data bytes found in the FIFO buffer. With the CRCReady flag setting to 1, an interrupt is requested with TxIRq being set. This supports interrupt driven usage of the CRC-Coprocessor. When CRCReady and TxIRq are set to 1, respectively, the content of the CRCResultLSB- and CRCResultMSB-register and the flag CRCErr is valid. The CRCResultLSB- and CRCResultMSB-register hold the content of the CRC register, the CRCErr flag indicates CRC validity for the processed data.
16.7 Error Handling during Command Execution If any error is detected during command execution, this is shown by setting the status flag Err in the PrimaryStatus Register. For information about the cause of the error, the -Processor may evaluate the status flags in the ErrorFlag Register.
Error Flag of the ErrorFlag Register AccessError FIFOOvl CRCErr FramingErr CollErr Related to Command WriteE2, ReadE2, LoadConfig Not related to a command Receive, Transceive, CalcCRC Receive, Transceive Receive, Transceive
Table 16-6: Error Flags Overview
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
17
TYPICAL APPLICATION
17.1 Circuit Diagram The figure below shows a typical application, where the antenna is direct connected to the SL RC400:
DVDD
Reset
AVDD
TVDD
DVDD Control Lines Processor Bus
RSTPD
AVDD
TVDD
L0
C1 C0 C2a
TX1
Processor
Data Bus
TVSS
IRQ
IRQ
SL RC400
C0 C2b
TX2
L0 C1 R1'
RX
R1 C3 R2
DVSS
OSCIN
OSCOUT AVSS
VMID
13.56 MHz 15 pF 15 pF
C4 100 nF
Figure 17-1: Circuit Diagram for Application Example: Direct Matched Antenna
The matching circuit consists of an EMC low pass filter, a receiving circuit, an antenna matching circuit and the antenna itself. For more detailed information about designing and tuning an antenna please refer to chapter 17.3.1.
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
17.2 Circuit Description 17.2.1 EMC LOW PASS FILTER The I*CODE system operates at a frequency of 13.56 MHz. This frequency is generated by a quartz oscillator to clock the SL RC400 and is also the basis for driving the antenna with the 13.56 MHz carrier frequenzy. This will not only cause emitted power at 13.56 MHz but will also emit power at higher harmonics. The international EMC regulations define the amplitude of the emitted power in a broad frequency range. Thus, an appropriate filtering of the output signal is necessary to fulfil these regulations. A multi-layer board it is strongly recommended to implement a low pass filter as shown in the circuit above. The low pass filter consists of the components L0 and C0. The values are given in table below. Note: To achieve best performance all components shall have at least the quality of the recommended ones. 17.2.2 RECEIVING CIRCUIT The internal receiving part of the SL RC400 uses a concept that benefits from both side-bands of the subcarrier load modulation of the label response. It is recommended to use the internally generated VMID potential as the input potential of pin RX. To provide a stable reference voltage a capacitance C4 to ground has to be connected to VMID. The receiving part of the reader needs a voltage divider connected between the RX and the VMID pin. Additionally, it is recommended to use a series capacitance between the antenna coil and the voltage divider. The circuit diagram above shows the recommended receiving circuit. The receiving circuit consists of the components R1, R2, C3 and C4. The values are given in the table below.
Components L0 C0 R1' R1 R2 C3 Value 1 H 5% 2 * 68 pF 2% 3.9 k 1% 560 1% 820 1% 1 nF 2% NP0 material Remark Magnetic shielded e.g. TDK NL322522T-1R0J NP0 material, Value depending on the antenna inductance
Table 17-1: Values for the EMC- Filter and Receiving Circuit Note: It is recommended not to use X7R material for the capacitors. 17.3 Calculation of the Antenna Coil Inductance The precise calculation of the antenna coils inductance is not practicable but the inductance can be estimated using the following formula. We recommend designing an antenna either with a circular or rectangular shape.
l 1, 8 L1 [nH ] = 2 l 1 [cm ] ln 1 - K N 1 D1
l1.............. Length of the conductor loop of one turn D1 ............ Diameter of the wire or width of the PCB conductor respectively K ............. Antenna Shape Factor (K = 1,07 for circular antennas and K = 1,47 for square antennas) N1 ............ Number of turns ln ............. Natural logarithm function 110 Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
17.3.1 IMPEDANCE MATCHING FOR DIRECTLY MATCHED ANTENNAS To design a matching circuit for a directly matched antenna we recommend to use the circuit shown in 17.1. The values for the capacitors C1 and C2a, C2b depend on the antenna's electrical properties and environmental influences. The values for the capacitors shown in the table below are guidelines. In fact, they are used as starting values for the tuning procedure.
Antenna Coil Inductance [H] 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 C1 [pF] 27 27 27 27 27 27 27 27 27 27 27 C2a [pF] 270 270 220 180 || 22 180 180 150 150 120 || 10 120 120 C2b [pF] 330 270 270 220 180 || 22 180 180 150 150 150 120
Table 17-2: Capacitance Values for the Matching Circuit
However, for optimum performance, the accurate values have to be found by the tuning, variation of the capacitance's C2x and C1. The above table assumes a stray capacitance of 15 pF of the antenna coil. The capacitors C1 and C2s should have a NP0 dielectric with a tolerance of +/-2 %. The actual values of the antenna inductance and capacitance depend on various parameters like: * * * * * antenna construction (Type of PCB) thickness of conductor distance between the windings shielding layer metal or ferrite in the near environment
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
18
TEST SIGNALS
18.1 General The SL RC400 allows different kind of signal measurements. These measurements can be used to check the internally generated and received signals using the possibilities of the serial signal switch as described in chapter 15. Furthermore, with the SL RC400 the user may select internal analog signals to measure them at pin AUX and internal digital signals to observe them on pin SIGOUT by register selections. These measurements can be helpful during the design-in phase to optimise the receiver's behaviour or for test purpose.
18.2 Measurements Using the Serial Signal Switch Using the serial signal switch at pin SIGOUT the user may observe data send to the label or data received from the label. The following tables give an overview of the different signals available.
SignalToSIGOUT 0 0 0 0 0 0 0 0 1
SIGOUTSelect 0 1 2 3 4 5 6 7 X
Signal routed to SIGOUT pin LOW HIGH Envelope Transmit NRZ Manchester with Subcarrier Manchester RFU RFU Digital Test signal
Table 18-1 Signal routed to SIGOUT pin
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
18.3 Analog Test-Signals The analog test signals may be routed to pin AUX by selecting them with the register bits TestAnaOutSel.
Value Signal Name Description
0 1 2 3 4 5 6 7 8 9 A B C D E F
Vmid Vbandgap VRxFollI VRxFollQ VRxAmpI VRxAmpQ VCorrNI VCorrNQ VCorrDI VCorrDQ VEvalL VEvalR VTemp RFU RFU RFU
Voltage at internal node Vmid Internal reference voltage generated by the band gap. Output signal from the demodulator using the I-clock. Output signal from the demodulator using the Q-clock. I-channel subcarrier signal amplified and filtered. Q-channel subcarrier signal amplified and filtered. Output signal of N-channel correlator fed by the I-channel subcarrier signal. Output signal of N-channel correlator fed by the Q-channel subcarrier signal. Output signal of D-channel correlator fed by the I-channel subcarrier signal. Output signal of D-channel correlator fed by the Q-channel subcarrier signal. Evaluation signal from the left half bit. Evaluation signal from the right half bit. Temperature voltage derived from band gap. Reserved for future use Reserved for future use Reserved for future use Table 18-2: Analog Test Signal Selection
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
18.4 Digital Test-Signals Digital test signals may be routed to pin SIGOUT by setting bit SignalToSIGOUT to 1. A digital test signal may be selected via the register bits TestDigiSignalSel in Register TestDigiSelect. The signals selected by a certain TestDigiSignalSel setting is shown in the table below:
TestDigiSignalSel F4 hex E4hex D4hex C4hex B5hex A5hex 96hex 00hex Signal Name s_data s_valid s_coll s_clock rd_sync wr_sync int_clock no test signal Data received from the label. Shows with 1, that the signals s_data and s_coll are valid. Shows with 1, that a collision has been detected in the current bit. Internal serial clock: during transmission, this is the coder-clock and during reception this is the receiver clock. Internal synchronised read signal (derived from the parallel -Processor interface). Internal synchronised write signal (derived from the parallel -Processor interface). Internal 13.56 MHz clock. output as defined by SIGOUTSelect are routed to pin SIGOUT. Description
Table 18-3: Digital Test Signal Selection
If no test signals are used, the value for the TestDigiSel-Register shall be 00hex . Note: All other values of TestDigiSignalSel are for production test purposes only.
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
18.5 Examples of Analog- and Digital Test Signals
Fig. 17 shows the answer of an I*CODE1 Label IC to a unselected read command using the Qclock receiving path. RX -Reference is given to show the Manchester modulated signal at the RX pin. This signal is demodulated and amplified in the receiver circuitry VRXAmpQ shows the amplified side band signal having used the QClock for demodulation. The signals VCorrDQ and VCorrNQ generated in the correlation circuitry are evaluated and digitised in the evaluation and digitizer circuitry. VEvalR and VEvalL show the evaluation signal of the right and left half bit. Finally, the digital test-signal S_data shows the received data which is send to the internal digital circuit and S_valid indicates that the received data stream is valid.
Receiving path Q-Clock
VrxAmpQ
VcorrDQ
VcorrNQ
VevalR
VevalL
Sdata
50sec/Dev.
SValid
500sec/Dev. Figure 17. Receiving path Q-Clock
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
19
ELECTRICAL CHARACTERISTICS
19.1 Absolute Maximum Ratings
SYMBOL Tamb,abs DVDD AVDD TVDD Vin,abs VRX,abs Absolute voltage on any digital pin to DVSS Absolute voltage on RX pin to AVSS -0.5 -0.5 DVDD + 0.5 AVDD + 0.5 V V DC Supply Voltages -0.5 6 V PARAMETER Ambient or Storage Temperature Range MIN -40 MAX +150 UNIT C
Table 19-1: Absolute Maximum Ratings
19.2 Operating Condition Range
SYMBOL Tamb DVDD AVDD TVDD PARAMETER Ambient Temperature Digital Supply Voltage Analog Supply Voltage Transmitter Supply Voltage DVSS = AVSS = TVSS = 0V CONDITIONS MIN -25 4.5 4.5 3.0 TYP +25 5.0 5.0 5.0 MAX +85 5.5 5.5 5.5 UNIT C V V V
Table 19-2: Operating Condition Range
19.3 Current Consumption
SYMBOL PARAMETER CONDITIONS Idle Command Stand By Mode IDVDD Digital Supply Current Soft Power Down Mode Hard Power Down Mode Idle Command, Receiver On Idle Command, Receiver Off IAVDD Analog Supply Current Stand By Mode Soft Power Down Mode Hard Power Down Mode Continuous Wave ITVDD Transmitter Supply Current TX1 and TX2 unconnected TX1RFEn, TX2RFEn = 1 TX1 and TX2 unconnected TX1RFEn, TX2RFEn = 0 4.5 65 MIN TYP 6 3 800 1 29 10 8 1 1 150 9 130 MAX UNIT mA mA A A mA mA mA A A mA mA A
Table 19-3: Current Consumption 117 Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
19.4 Pin Characteristics 19.4.1 INPUT PIN CHARACTERISTICS Pins D0 to D7, A0 and A1 have TTL input characteristics and behave as defined in the following table.
SYMBOL ILeak VT PARAMETER Input Leakage Current Threshold CONDITIONS MIN -1.0 0.8 MAX +1.0 2.0 UNIT A V
Table 19-4: Standard Input Pin Characteristics
The digital input pins NCS, NWR, NRD, ALE and A2 have Schmitt-Trigger characteristics, and behave as defined in the following table.
SYMBOL ILeak VT+ VTPARAMETER Input Leakage Current Positive-Going Threshold Negative-Going Threshold CONDITIONS MIN -1.0 1.4 0.8 MAX +1.0 2.0 1.3 UNIT A V V
Table 19-5: Schmitt-Trigger Input Pin Characteristics
Pin RSTPD has Schmitt-Trigger CMOS characteristics. In addition, it is internally filtered with an RC-lowpass filter, which causes a relevant propagation delay for the reset signal:
SYMBOL ILeak VT+ VTtRSTPD,p PARAMETER Input Leakage Current Positive-Going Threshold Negative-Going Threshold Propagation Delay CONDITIONS MIN -1.0 0.65 DVDD 0.25 DVDD MAX +1.0 0.75 DVDD 0.4 DVDD 20 UNIT A V V s
Table 19-6: RSTPD Input Pin Characteristics
The analog input pin RX has the following input capacitance:
SYMBOL CRX PARAMETER Input Capacitance CONDITIONS MIN MAX 15 UNIT pF
Table 19-7: RX Input Capacitance
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I*CODE Reader IC
SL RC400
19.4.2 DIGITAL OUTPUT PIN CHARACTERISTICS Pins D0 to D7, SIGOUT and IRQ have TTL output characteristics and behave as defined in the following table.
SYMBOL VOH PARAMETER Output Voltage HIGH CONDITIONS DVDD = 5 V, IOH = -1 mA DVDD = 5 V, IOH = -10 mA VOL IO Output Voltage LOW Output Current source or sink DVDD = 5 V, IOL = 1 mA DVDD = 5 V, IOL = 10 mA DVDD = 5 V MIN 2.4 2.4 TYP 4.9 4.2 25 250 400 400 10 MAX UNIT V V mV mV mA
Table 19-8:Digital Output Pin Characteristics Note: IRQ pin may also be configured as open collector. In that case the values for VOH do not apply.
19.4.3 ANTENNA DRIVER OUTPUT PIN CHARACTERISTICS The source conductance of the antenna driver pins TX1 and TX2 for driving the HIGH level can be configured via GsCfgCW in the CwConductance Register, while their source conductance for driving the LOW level is constant. For the default configuration, the output characteristic is specified below:
SYMBOL VOH PARAMETER Output Voltage HIGH CONDITIONS TVDD = 5.0 V, I OL = 20 mA TVDD = 5.0 V, I OL = 100 mA VOL ITX Output Voltage LOW Transmitter Output Current TVDD = 5.0 V, I OL = 20 mA TVDD = 5.0 V, I OL = 100 mA Continuous Wave MIN TYP 4.97 4.85 30 150 200 MAX UNIT V V mV mV mApeak
Table 19-9:Antenna Driver Output Pin Characteristics
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
19.5 AC Electrical Characteristics 19.5.1 AC SYMBOLS Each timing symbol has five characters. The first character is always 't' for time. The other characters indicate the name of a signal or the logic state of that signal (depending on position):
Designation: A D W R L C S Signal: address data NWR or nWait NRD or R/NW or nWrite ALE or AS NCS NDS or nDStrb and nAStrb Designation: H L Z X V Logic Level: HIGH LOW high impedance any level or data any valid signal or data
Example: tAVLL = time for address valid to ALE low
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
19.5.2 AC OPERATING SPECIFICATION 19.5.2.1 Bus Timing for Separated Read/Write Strobe
SYMBOL tLHLL tAVLL tLLAX tLLWL tCLWL tWHCH tRLDV tRHDZ tWLDV tWHDX tWLWH tAVWL tWHAX tWHWL PARAMETER ALE pulse width Multiplexed Address Bus valid to ALE low (Address Set Up Time) Multiplexed Address Bus valid after ALE low (Address Hold Time) ALE low to NWR, NRD low NCS low to NRD, NWR low NRD, NWR high to NCS high NRD low to DATA valid NRD high to DATA high impedance NWR low to DATA valid DATA hold after NWR high (Data Hold Time) NRD, NWR pulse width Separated Address Bus valid to NRD, NWR low (Set Up Time) Separated Address Bus valid after NWR high (Hold Time) period between sequenced read / write accesses 8 65 30 8 150 MIN 20 15 8 15 0 0 65 20 35 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 19-10: Timing Specification for Separated Read/Write Strobe
tLHLL
ALE
tCLWL
tWHCH
NCS
tLLWL tWHWL tWLWH tWHWL
NWR NRD
tWLDV tRLDV tWHDX tRHDZ
tAVLL
tLLAX
D0 ... D7
Multiplexed Addressbus
A0 ... A2
D0 ... D7
tAVWL
t WHAX
A0 ... A2
Separated Addressbus
A0 ... A2
Figure 19-1: Timing Diagram for Separated Read/Write Strobe
Note: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don't care. For the multiplexed address and data bus the address lines A0 to A2 have to be connected as described in 4.3.
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
19.5.2.2 Bus Timing for Common Read/Write Strobe
SYMBOL tLHLL tAVLL tLLAX tLLSL tCLSL tSHCH tSLDV,R tSHDZ tSLDV,W tSHDX tSHRX tSLSH tAVSL tSHAX tSHSL tRVSL PARAMETER AS pulse width Multiplexed Address Bus valid to AS low (Address Set Up Time) Multiplexed Address Bus valid after AS low (Address Hold Time) AS low to NDS low NCS low to NDS low NDS high to NCS high NDS low to DATA valid (for read cycle) NDS low to DATA high impedance (read cycle) NDS low to DATA valid (for write cycle) DATA hold after NDS high (write cycle, Hold Time) R/NW hold after NDS high NDS pulse width Separated Address Bus valid to NDS low (Hold Time) Separated Address Bus valid after NDS high (Set Up Time) period between sequenced read/write accesses R/NW valid to NDS low MIN 20 15 8 15 0 0 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
65 20 35 8 8 65 30 8 150 8
Table 19-11: Timing Specification for Common Read/Write Strobe
tLHLL
ALE
tCLSL
tSHCH
NCS
tRVSL
tSHRX
R/NW
tLLSL tSHSL tSLSH tSHSL
NDS
tAVLL
tLLAX
tSLDV,R tSLDV,W
tSHDX tSHDZ
D0 ... D7
Multiplexed Addressbus
A0 ... A2
D0 ... D7
tAVSL
tSHAX
A0 ... A2
Separated Addressbus
A0 ... A2
Figure 19-2: Timing Diagram for Common Read/Write Strobe
Note: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don't care. For the multiplexed address and data bus the address lines A0 to A2 have to be connected as described in 4.3.
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
19.5.2.3 Bus Timing for EPP
SYMBOL tLLLH tAVLH tLHAX tCLSL tSHCH tSLDV,R tSHDZ tSLDV,W tSHDX tSHRX tSLSH tRVSL tSLWH tSHWL PARAMETER nAStrb pulse width Multiplexed Address Bus valid to nAStrb high (Set Up Time) Multiplexed Address Bus valid after nAStrb high (Hold Time) NCS low to nDStrb low nDStrb high to NCS high nDStrb low to DATA valid (read cycle) nDStrb low to DATA high impedance (read cycle) nDStrb low to DATA valid (write cycle, Set up Time) DATA hold after nDStrb high (write cycle, Hold Time) nWrite hold after nDStrb high nDStrb pulse width nWrite valid to nDStrb low nDStrb low to nWait high nDStrb high to nWait low 8 8 65 8 75 75 MIN 20 15 8 0 0 65 20 35 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 19-12: Timing Specification for Common Read/Write Strobe
t CLSL
tSHCH
NCS
tRVSL
tSHRX
nWrite
t SLSH
nDStrb nAStrb
t SLDV,R t SLDV,W tSHDX tSHDZ
D0 ... D7
D0 ... D7 A0 ... A7
tSLWH
tSHWL
nWait
Figure 19-3: Timing Diagram for Common Read/Write Strobe Remark: The figure does not distinguish between the Address Write Cycle and a Data Write Cycle. Take in account, that timings for the Address Write and Data Write Cycle different. For the EPP-Mode the address lines A0 to A2 have to be connected as described in 4.3.
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
19.5.3 CLOCK FREQUENCY The clock input is pin 1, OSCIN.
PARAMETER Clock Frequency (checked by the clock filter) Duty Cycle of Clock Frequency Jitter of Clock Edges SYMBOL fOSCIN dFEC tjitter 40 MIN TYP 13.56 50 60 10 MAX UNIT MHz % ps
The clock applied to the SL RC400 acts as time basis for the coder and decoder of the synchronous system. Therefore stability of clock frequency is an important factor for proper performance. To obtain highest performance, clock jitter shall be as small as possible. This is best achieved using the internal oscillator buffer with the recommended circuitry (see 12).
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
20
E PROM CHARACTERISTICS
2
The EPROM has a size of 8x16x8 = 1.024 bit.
SYMBOL tEEEndurance tEERetention tEEErase tEEWrite PARAMETER Data Endurance Data Retention Erase Time Write Time Tamb 55C CONDITIONS MIN 100.000 10 2.9 2.9 MAX UNIT erase/write cycles years ms ms
Table 20-1:EPROM Characteristics
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
21
PACKAGE OUTLINES
21.1 SO32
SO32: plastic small outline package; 32 leads; body width 7.5 mm SOT287-1
D
E
A
X
c y HE vM A
Z 32 17
Q A2 pin 1 index Lp 1 e bp 16 wM L detail X A1 (A3 ) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 2.65 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 bp 0.49 0.36 c 0.27 0.18 D(1) 20.7 20.3 E (1) 7.6 7.4 e 1.27 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.2 1.0 v 0.25 w 0.25 y 0.1 Z (1) 0.95 0.55
o
0.012 0.096 inches 0.10 0.01 0.004 0.086
0.02 0.011 0.81 0.01 0.007 0.80
0.30 0.419 0.043 0.047 0.050 0.055 0.01 0.29 0.394 0.016 0.039
0.037 0.01 0.004 0.022
8 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT287-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-25 97-05-22
Figure 21-1: Outline and Dimension of SL RC400 in SO32 126
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Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
22
TERMS AND ABBREVIATIONS Description: Micro Processor Electrically Erasable Programmable Read Only Memory End of Frame Frame Waiting Time: maximum time delay between last bit transmitted by the reader and first bit received from the label's response. A family of hard-wired logic contactless label ICs. The protocol of these labels is according to I*CODE1 and ISO 15693. On top they use a fixed set of commands. Power On Reset: triggers a reset, caused by a rising edge on a supply pin. Read Only Memory Start of Frame
Designation: -Processor EPROM EOF FWT I?CODE
POR ROM SOF
127
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
23
DEFINITIONS
Data sheet status Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics section of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. This data sheet contains final product specifications.
24
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so on their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
128
Preliminary
Philips Semiconductors
Product Specification Rev. 2.0 November 2001
I*CODE Reader IC
SL RC400
25
REVISION HISTORY
DATE CPCN PAGE DESCRIPTION First published version 14.11.01 Preliminary version
REVISION 1.0 2.0
Table 25-1: Document Versions Up to Revision 1.0
129
Preliminary
Philips Semiconductors - a worldwide company
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Published by:
Philips Semiconductors Gratkorn GmbH, Mikron-Weg 1, A-8101 Gratkorn, Austria Fax: +43 3124 299 - 270
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Internet: http://www.semiconductors.philips.com Building BE-p, P.O.Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax: +3140 27 24825 (c) Philips Electronics N.V. 1997 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without any notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. SCB52
Philips Semiconductors

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